forked from OSchip/llvm-project
54 lines
1.5 KiB
YAML
54 lines
1.5 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
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---
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name: bitreverse_i32_ss
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0
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; CHECK-LABEL: name: bitreverse_i32_ss
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; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; CHECK: [[S_BREV_B32_:%[0-9]+]]:sreg_32 = S_BREV_B32 [[COPY]]
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; CHECK: S_ENDPGM 0, implicit [[S_BREV_B32_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = G_BITREVERSE %0
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S_ENDPGM 0, implicit %1
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...
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---
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name: bitreverse_i32_vv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: bitreverse_i32_vv
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; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK: [[V_BFREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_BFREV_B32_e64 [[COPY]], implicit $exec
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; CHECK: S_ENDPGM 0, implicit [[V_BFREV_B32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = G_BITREVERSE %0
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S_ENDPGM 0, implicit %1
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...
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---
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name: bitreverse_i32_vs
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0
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; CHECK-LABEL: name: bitreverse_i32_vs
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; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; CHECK: [[V_BFREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_BFREV_B32_e64 [[COPY]], implicit $exec
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; CHECK: S_ENDPGM 0, implicit [[V_BFREV_B32_e64_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = G_BITREVERSE %0
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S_ENDPGM 0, implicit %1
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...
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