forked from OSchip/llvm-project
198 lines
10 KiB
LLVM
198 lines
10 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
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; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
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; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
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; WARN-NOT: warning
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;
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; ST1H, ST1W, ST1D: base + 32-bit scaled offset, sign (sxtw) or zero
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; (uxtw) extended to 64 bits.
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; e.g. st1h { z0.d }, p0, [x0, z1.d, uxtw #1]
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;
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; ST1H
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define void @sst1h_s_uxtw(<vscale x 4 x i32> %data, <vscale x 4 x i1> %pg, i16* %base, <vscale x 4 x i32> %indices) {
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; CHECK-LABEL: sst1h_s_uxtw:
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; CHECK: st1h { z0.s }, p0, [x0, z1.s, uxtw #1]
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; CHECK-NEXT: ret
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%data_trunc = trunc <vscale x 4 x i32> %data to <vscale x 4 x i16>
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call void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv4i16(<vscale x 4 x i16> %data_trunc,
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<vscale x 4 x i1> %pg,
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i16* %base,
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<vscale x 4 x i32> %indices)
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ret void
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}
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define void @sst1h_s_sxtw(<vscale x 4 x i32> %data, <vscale x 4 x i1> %pg, i16* %base, <vscale x 4 x i32> %indices) {
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; CHECK-LABEL: sst1h_s_sxtw:
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; CHECK: st1h { z0.s }, p0, [x0, z1.s, sxtw #1]
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; CHECK-NEXT: ret
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%data_trunc = trunc <vscale x 4 x i32> %data to <vscale x 4 x i16>
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call void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv4i16(<vscale x 4 x i16> %data_trunc,
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<vscale x 4 x i1> %pg,
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i16* %base,
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<vscale x 4 x i32> %indices)
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ret void
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}
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define void @sst1h_d_uxtw(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, i16* %base, <vscale x 2 x i32> %indices) {
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; CHECK-LABEL: sst1h_d_uxtw:
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; CHECK: st1h { z0.d }, p0, [x0, z1.d, uxtw #1]
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; CHECK-NEXT: ret
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%data_trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i16>
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call void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv2i16(<vscale x 2 x i16> %data_trunc,
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<vscale x 2 x i1> %pg,
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i16* %base,
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<vscale x 2 x i32> %indices)
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ret void
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}
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define void @sst1h_d_sxtw(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, i16* %base, <vscale x 2 x i32> %indices) {
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; CHECK-LABEL: sst1h_d_sxtw:
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; CHECK: st1h { z0.d }, p0, [x0, z1.d, sxtw #1]
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; CHECK-NEXT: ret
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%data_trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i16>
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call void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv2i16(<vscale x 2 x i16> %data_trunc,
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<vscale x 2 x i1> %pg,
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i16* %base,
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<vscale x 2 x i32> %indices)
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ret void
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}
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; ST1W
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define void @sst1w_s_uxtw(<vscale x 4 x i32> %data, <vscale x 4 x i1> %pg, i32* %base, <vscale x 4 x i32> %indices) {
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; CHECK-LABEL: sst1w_s_uxtw:
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; CHECK: st1w { z0.s }, p0, [x0, z1.s, uxtw #2]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv4i32(<vscale x 4 x i32> %data,
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<vscale x 4 x i1> %pg,
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i32* %base,
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<vscale x 4 x i32> %indices)
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ret void
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}
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define void @sst1w_s_sxtw(<vscale x 4 x i32> %data, <vscale x 4 x i1> %pg, i32* %base, <vscale x 4 x i32> %indices) {
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; CHECK-LABEL: sst1w_s_sxtw:
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; CHECK: st1w { z0.s }, p0, [x0, z1.s, sxtw #2]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv4i32(<vscale x 4 x i32> %data,
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<vscale x 4 x i1> %pg,
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i32* %base,
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<vscale x 4 x i32> %indices)
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ret void
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}
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define void @sst1w_d_uxtw(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, i32* %base, <vscale x 2 x i32> %indices) {
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; CHECK-LABEL: sst1w_d_uxtw:
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; CHECK: st1w { z0.d }, p0, [x0, z1.d, uxtw #2]
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; CHECK-NEXT: ret
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%data_trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i32>
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call void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv2i32(<vscale x 2 x i32> %data_trunc,
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<vscale x 2 x i1> %pg,
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i32* %base,
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<vscale x 2 x i32> %indices)
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ret void
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}
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define void @sst1w_d_sxtw(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, i32* %base, <vscale x 2 x i32> %indices) {
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; CHECK-LABEL: sst1w_d_sxtw:
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; CHECK: st1w { z0.d }, p0, [x0, z1.d, sxtw #2]
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; CHECK-NEXT: ret
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%data_trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i32>
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call void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv2i32(<vscale x 2 x i32> %data_trunc,
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<vscale x 2 x i1> %pg,
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i32* %base,
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<vscale x 2 x i32> %indices)
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ret void
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}
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define void @sst1w_s_uxtw_float(<vscale x 4 x float> %data, <vscale x 4 x i1> %pg, float* %base, <vscale x 4 x i32> %indices) {
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; CHECK-LABEL: sst1w_s_uxtw_float:
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; CHECK: st1w { z0.s }, p0, [x0, z1.s, uxtw #2]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv4f32(<vscale x 4 x float> %data,
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<vscale x 4 x i1> %pg,
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float* %base,
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<vscale x 4 x i32> %indices)
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ret void
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}
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define void @sst1w_s_sxtw_float(<vscale x 4 x float> %data, <vscale x 4 x i1> %pg, float* %base, <vscale x 4 x i32> %indices) {
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; CHECK-LABEL: sst1w_s_sxtw_float:
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; CHECK: st1w { z0.s }, p0, [x0, z1.s, sxtw #2]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv4f32(<vscale x 4 x float> %data,
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<vscale x 4 x i1> %pg,
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float* %base,
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<vscale x 4 x i32> %indices)
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ret void
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}
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; ST1D
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define void @sst1d_d_uxtw(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, i64* %base, <vscale x 2 x i32> %indices) {
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; CHECK-LABEL: sst1d_d_uxtw:
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; CHECK: st1d { z0.d }, p0, [x0, z1.d, uxtw #3]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv2i64(<vscale x 2 x i64> %data,
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<vscale x 2 x i1> %pg,
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i64* %base,
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<vscale x 2 x i32> %indices)
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ret void
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}
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define void @sst1d_d_sxtw(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, i64* %base, <vscale x 2 x i32> %indices) {
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; CHECK-LABEL: sst1d_d_sxtw:
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; CHECK: st1d { z0.d }, p0, [x0, z1.d, sxtw #3]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv2i64(<vscale x 2 x i64> %data,
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<vscale x 2 x i1> %pg,
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i64* %base,
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<vscale x 2 x i32> %indices)
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ret void
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}
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define void @sst1d_d_uxtw_double(<vscale x 2 x double> %data, <vscale x 2 x i1> %pg, double* %base, <vscale x 2 x i32> %indices) {
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; CHECK-LABEL: sst1d_d_uxtw_double:
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; CHECK: st1d { z0.d }, p0, [x0, z1.d, uxtw #3]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv2f64(<vscale x 2 x double> %data,
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<vscale x 2 x i1> %pg,
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double* %base,
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<vscale x 2 x i32> %indices)
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ret void
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}
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define void @sst1d_d_sxtw_double(<vscale x 2 x double> %data, <vscale x 2 x i1> %pg, double* %base, <vscale x 2 x i32> %indices) {
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; CHECK-LABEL: sst1d_d_sxtw_double:
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; CHECK: st1d { z0.d }, p0, [x0, z1.d, sxtw #3]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv2f64(<vscale x 2 x double> %data,
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<vscale x 2 x i1> %pg,
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double* %base,
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<vscale x 2 x i32> %indices)
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ret void
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}
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; ST1H
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declare void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i1>, i16*, <vscale x 4 x i32>)
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declare void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i1>, i16*, <vscale x 2 x i32>)
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declare void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i1>, i16*, <vscale x 4 x i32>)
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declare void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i1>, i16*, <vscale x 2 x i32>)
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; ST1W
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declare void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, i32*, <vscale x 4 x i32>)
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declare void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i1>, i32*, <vscale x 2 x i32>)
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declare void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, i32*, <vscale x 4 x i32>)
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declare void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i1>, i32*, <vscale x 2 x i32>)
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declare void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, float*, <vscale x 4 x i32>)
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declare void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, float*, <vscale x 4 x i32>)
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; ST1D
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declare void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i64*, <vscale x 2 x i32>)
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declare void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i64*, <vscale x 2 x i32>)
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declare void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, double*, <vscale x 2 x i32>)
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declare void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, double*, <vscale x 2 x i32>)
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