forked from OSchip/llvm-project
195 lines
5.8 KiB
YAML
195 lines
5.8 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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#
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# Test widening and narrowing on test bit operations using subregister copies
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# or SUBREG_TO_REG.
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--- |
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@glob = external unnamed_addr global i1, align 4
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define void @s1_no_copy() { ret void }
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define void @s16_no_copy() { ret void }
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define void @p0_no_copy() { ret void }
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define void @widen_s32_to_s64() { ret void }
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define void @widen_s16_to_s64() { ret void }
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define void @narrow_s64_to_s32() { ret void }
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...
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---
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name: s1_no_copy
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: s1_no_copy
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; CHECK: bb.0:
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; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK: %narrow:gpr32 = IMPLICIT_DEF
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; CHECK: TBNZW %narrow, 0, %bb.1
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; CHECK: B %bb.0
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; CHECK: bb.1:
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; CHECK: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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%narrow:gpr(s1) = G_IMPLICIT_DEF
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; There should be no copy here, because the s1 can be selected to a GPR32.
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G_BRCOND %narrow(s1), %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR
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...
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---
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name: s16_no_copy
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: s16_no_copy
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; CHECK: bb.0:
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; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK: %narrow:gpr32 = IMPLICIT_DEF
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; CHECK: TBNZW %narrow, 0, %bb.1
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; CHECK: B %bb.0
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; CHECK: bb.1:
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; CHECK: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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%narrow:gpr(s16) = G_IMPLICIT_DEF
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%trunc:gpr(s1) = G_TRUNC %narrow(s16)
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; Look through the G_TRUNC to get the G_IMPLICIT_DEF. We don't need a
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; SUBREG_TO_REG here, because the s16 will end up on a 32-bit register.
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G_BRCOND %trunc(s1), %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR
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...
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---
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name: p0_no_copy
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: p0_no_copy
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; CHECK: bb.0:
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; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK: %glob:gpr64common = MOVaddr target-flags(aarch64-page) @glob, target-flags(aarch64-pageoff, aarch64-nc) @glob
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; CHECK: %load:gpr32 = LDRBBui %glob, 0 :: (dereferenceable load 1 from @glob, align 4)
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; CHECK: TBNZW %load, 0, %bb.1
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; CHECK: B %bb.0
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; CHECK: bb.1:
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; CHECK: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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%glob:gpr(p0) = G_GLOBAL_VALUE @glob
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%load:gpr(s8) = G_LOAD %glob(p0) :: (dereferenceable load 1 from @glob, align 4)
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%trunc:gpr(s1) = G_TRUNC %load(s8)
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; Look through G_TRUNC to get the load. The load is into a s8, which will
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; be selected to a GPR32, so we don't need a copy.
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G_BRCOND %trunc(s1), %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR
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...
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---
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name: widen_s32_to_s64
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: widen_s32_to_s64
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; CHECK: bb.0:
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; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK: liveins: $w0
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; CHECK: %reg:gpr32all = COPY $w0
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %reg, %subreg.sub_32
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; CHECK: TBZX [[SUBREG_TO_REG]], 33, %bb.1
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; CHECK: B %bb.0
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; CHECK: bb.1:
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; CHECK: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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liveins: $w0
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%reg:gpr(s32) = COPY $w0
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%zext:gpr(s64) = G_ZEXT %reg(s32)
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%bit:gpr(s64) = G_CONSTANT i64 8589934592
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%zero:gpr(s64) = G_CONSTANT i64 0
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%and:gpr(s64) = G_AND %zext, %bit
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%cmp:gpr(s32) = G_ICMP intpred(eq), %and(s64), %zero
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; We should widen using a SUBREG_TO_REG here, because we need a TBZX to get
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; bit 33. The subregister should be sub_32.
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%trunc:gpr(s1) = G_TRUNC %cmp(s32)
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G_BRCOND %trunc(s1), %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR
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...
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---
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name: widen_s16_to_s64
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: widen_s16_to_s64
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; CHECK: bb.0:
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; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK: %reg:gpr32 = IMPLICIT_DEF
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %reg, %subreg.sub_32
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; CHECK: TBZX [[SUBREG_TO_REG]], 33, %bb.1
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; CHECK: B %bb.0
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; CHECK: bb.1:
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; CHECK: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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%reg:gpr(s16) = G_IMPLICIT_DEF
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%zext:gpr(s64) = G_ZEXT %reg(s16)
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%bit:gpr(s64) = G_CONSTANT i64 8589934592
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%zero:gpr(s64) = G_CONSTANT i64 0
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%and:gpr(s64) = G_AND %zext, %bit
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%cmp:gpr(s32) = G_ICMP intpred(eq), %and(s64), %zero
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; We should widen using a SUBREG_TO_REG here, because we need a TBZX to get
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; bit 33. The subregister should be sub_32, because s16 will end up on a
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; GPR32.
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%trunc:gpr(s1) = G_TRUNC %cmp(s32)
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G_BRCOND %trunc(s1), %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR
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...
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---
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name: narrow_s64_to_s32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: narrow_s64_to_s32
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; CHECK: bb.0:
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; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK: liveins: $x0
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; CHECK: %wide:gpr64all = COPY $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %wide.sub_32
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
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; CHECK: TBNZW [[COPY1]], 0, %bb.1
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; CHECK: B %bb.0
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; CHECK: bb.1:
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; CHECK: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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liveins: $x0
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%wide:gpr(s64) = COPY $x0
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; We should narrow using a subregister copy here.
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%trunc:gpr(s1) = G_TRUNC %wide(s64)
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G_BRCOND %trunc(s1), %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR
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