forked from OSchip/llvm-project
151 lines
4.2 KiB
YAML
151 lines
4.2 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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#
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# Test that we can produce a tbz when we have a sgt compare against -1.
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#
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# The bit tested should be the size of the test register minus 1.
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#
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...
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---
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name: tbzx_sgt
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alignment: 4
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legalized: true
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regBankSelected: true
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body: |
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; CHECK-LABEL: name: tbzx_sgt
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; CHECK: bb.0:
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; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK: %copy:gpr64 = COPY $x0
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; CHECK: TBZX %copy, 63, %bb.1
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; CHECK: B %bb.0
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; CHECK: bb.1:
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; CHECK: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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liveins: $x0
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%copy:gpr(s64) = COPY $x0
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%negative_one:gpr(s64) = G_CONSTANT i64 -1
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%cmp:gpr(s32) = G_ICMP intpred(sgt), %copy(s64), %negative_one
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%cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
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G_BRCOND %cmp_trunc(s1), %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR
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...
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---
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name: tbzw_sgt
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alignment: 4
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legalized: true
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regBankSelected: true
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body: |
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; CHECK-LABEL: name: tbzw_sgt
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; CHECK: bb.0:
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; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK: %copy:gpr32 = COPY $w0
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; CHECK: TBZW %copy, 31, %bb.1
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; CHECK: B %bb.0
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; CHECK: bb.1:
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; CHECK: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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liveins: $x0
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%copy:gpr(s32) = COPY $w0
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%negative_one:gpr(s32) = G_CONSTANT i32 -1
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%cmp:gpr(s32) = G_ICMP intpred(sgt), %copy(s32), %negative_one
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%cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
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G_BRCOND %cmp_trunc(s1), %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR
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...
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---
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name: no_tbz_not_negative_one
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alignment: 4
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legalized: true
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regBankSelected: true
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body: |
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; CHECK-LABEL: name: no_tbz_not_negative_one
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; CHECK: bb.0:
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; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK: %copy:gpr32sp = COPY $w0
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; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %copy, 1, 0, implicit-def $nzcv
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; CHECK: Bcc 12, %bb.1, implicit $nzcv
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; CHECK: B %bb.0
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; CHECK: bb.1:
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; CHECK: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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liveins: $x0
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%copy:gpr(s32) = COPY $w0
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%one:gpr(s32) = G_CONSTANT i32 1
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%cmp:gpr(s32) = G_ICMP intpred(sgt), %copy(s32), %one
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%cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
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G_BRCOND %cmp_trunc(s1), %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR
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...
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---
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name: dont_fold_and
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alignment: 4
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legalized: true
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regBankSelected: true
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body: |
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; CHECK-LABEL: name: dont_fold_and
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; CHECK: bb.0:
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; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK: %copy:gpr64 = COPY $x0
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; CHECK: %and:gpr64sp = ANDXri %copy, 8000
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; CHECK: [[ADDSXri:%[0-9]+]]:gpr64 = ADDSXri %and, 1, 0, implicit-def $nzcv
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; CHECK: Bcc 12, %bb.1, implicit $nzcv
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; CHECK: B %bb.0
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; CHECK: bb.1:
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; CHECK: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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liveins: $x0
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%copy:gpr(s64) = COPY $x0
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%bit:gpr(s64) = G_CONSTANT i64 8
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%negative_one:gpr(s64) = G_CONSTANT i64 -1
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%c:gpr(s64) = G_CONSTANT i64 8
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%and:gpr(s64) = G_AND %copy, %bit
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%cmp:gpr(s32) = G_ICMP intpred(sgt), %and(s64), %negative_one
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%cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
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G_BRCOND %cmp_trunc(s1), %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR
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...
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---
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name: dont_commute
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alignment: 4
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legalized: true
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regBankSelected: true
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body: |
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; CHECK-LABEL: name: dont_commute
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; CHECK: bb.0:
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; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK: %copy:gpr64 = COPY $x0
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; CHECK: %negative_one:gpr64 = MOVi64imm -1
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; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %negative_one, %copy, implicit-def $nzcv
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; CHECK: Bcc 12, %bb.1, implicit $nzcv
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; CHECK: B %bb.0
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; CHECK: bb.1:
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; CHECK: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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liveins: $x0
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%copy:gpr(s64) = COPY $x0
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%negative_one:gpr(s64) = G_CONSTANT i64 -1
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%cmp:gpr(s32) = G_ICMP intpred(sgt), %negative_one, %copy(s64)
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%cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
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G_BRCOND %cmp_trunc(s1), %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR
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