forked from OSchip/llvm-project
38 lines
1.0 KiB
YAML
38 lines
1.0 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64"
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define i8 @load_acq_i8(i8* %ptr) {
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%v = load atomic i8, i8* %ptr acquire, align 8
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ret i8 %v
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}
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...
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---
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name: load_acq_i8
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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machineFunctionInfo: {}
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: load_acq_i8
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[LDARB:%[0-9]+]]:gpr32 = LDARB [[COPY]] :: (load acquire 1 from %ir.ptr, align 8)
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; CHECK: $w0 = COPY [[LDARB]]
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; CHECK: RET_ReallyLR implicit $w0
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%0:gpr(p0) = COPY $x0
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%2:gpr(s32) = G_LOAD %0(p0) :: (load acquire 1 from %ir.ptr, align 8)
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$w0 = COPY %2(s32)
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RET_ReallyLR implicit $w0
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...
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