llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fma.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc %s -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=regbankselect -o - | FileCheck %s
...
---
name: fma_f32
alignment: 4
legalized: true
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
bb.0:
liveins: $s0, $s1, $s2
; CHECK-LABEL: name: fma_f32
; CHECK: liveins: $s0, $s1, $s2
; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
; CHECK: [[COPY1:%[0-9]+]]:fpr(s32) = COPY $s1
; CHECK: [[COPY2:%[0-9]+]]:fpr(s32) = COPY $s2
; CHECK: [[FMA:%[0-9]+]]:fpr(s32) = nnan ninf nsz arcp contract afn reassoc G_FMA [[COPY]], [[COPY1]], [[COPY2]]
; CHECK: $s0 = COPY [[FMA]](s32)
; CHECK: RET_ReallyLR implicit $s0
%0:_(s32) = COPY $s0
%1:_(s32) = COPY $s1
%2:_(s32) = COPY $s2
%3:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FMA %0, %1, %2
$s0 = COPY %3(s32)
RET_ReallyLR implicit $s0
...
---
name: fma_f64
alignment: 4
legalized: true
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
bb.0:
liveins: $d0, $d1, $d2
; CHECK-LABEL: name: fma_f64
; CHECK: liveins: $d0, $d1, $d2
; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr(s64) = COPY $d1
; CHECK: [[COPY2:%[0-9]+]]:fpr(s64) = COPY $d2
; CHECK: [[FMA:%[0-9]+]]:fpr(s64) = nnan ninf nsz arcp contract afn reassoc G_FMA [[COPY]], [[COPY1]], [[COPY2]]
; CHECK: $d0 = COPY [[FMA]](s64)
; CHECK: RET_ReallyLR implicit $d0
%0:_(s64) = COPY $d0
%1:_(s64) = COPY $d1
%2:_(s64) = COPY $d2
%3:_(s64) = nnan ninf nsz arcp contract afn reassoc G_FMA %0, %1, %2
$d0 = COPY %3(s64)
RET_ReallyLR implicit $d0
...