llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/no-regclass.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=aarch64-apple-ios -global-isel -start-before=legalizer -stop-after=instruction-select %s -o - | FileCheck %s
# We run the legalizer to combine the trivial EXTRACT_SEQ pair, leaving %1 and
# %2 orphaned after instruction-selection (no instructions define or use
# them). This shouldn't be a problem.
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
define void @unused_reg() { ret void }
---
name: unused_reg
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0
; CHECK-LABEL: name: unused_reg
; CHECK: liveins: $w0
; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY $w0
; CHECK: $w0 = COPY [[COPY]]
%0:gpr(s32) = COPY $w0
%1:gpr(s64) = G_MERGE_VALUES %0(s32), %0(s32)
%2:gpr(s32), %3:gpr(s32) = G_UNMERGE_VALUES %1(s64)
$w0 = COPY %2(s32)
...