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llvm-project/llvm/test/CodeGen/AArch64/GlobalISel
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Amara Emerson ca7fdf7ce0 [AArch64][GlobalISel] Add pre-isel lowering to convert p0 G_DUPs to use s64. 
This uses the same reasoning as other similar conversions just before selection,
without it we miss out on selection because the importer considers s64 and p0
distinct types.
 		2020-11-23 22:59:35 -08:00
..
arm64-callingconv-ios.ll [AArch64] Provide Darwin variants of most calling conventions 2020-05-20 16:03:48 -07:00
arm64-callingconv.ll [AArch64][GlobalISel] Fix sub-64b stack parameter passing on Darwin. 2020-04-24 13:56:43 -07:00
arm64-fallback.ll [AArch64][GlobalISel] Make G_EXTRACT_VECTOR_ELT of <2 x p0> legal. 2020-11-20 14:07:45 -08:00
arm64-irtranslator-fmuladd.ll
…
arm64-irtranslator-gep.ll [GlobalISel][IRTranslator] Follow convention and put constant offset of getelementptr arithmetic on RHS. 2020-01-29 11:37:19 -08:00
arm64-irtranslator-stackprotect.ll
…
arm64-irtranslator-switch.ll [GlobalISel][IRTranslator] Generate better conditional branch lowering. 2020-09-09 13:16:11 -07:00
arm64-irtranslator.ll Try to fix buildbots after d3205bbca3 2020-10-26 11:49:21 +01:00
arm64-regbankselect.mir GlobalISel: Verify G_BITCAST changes the type 2020-07-08 17:16:27 -04:00
artifact-combine-unmerge.mir [GlobalISel] LegalizationArtifactCombiner: Fix a bug in tryCombineMerges 2020-02-14 10:45:58 -08:00
builtin-return-address-pacret.ll Reapply "RegAllocFast: Rewrite and improve" 2020-09-30 10:35:25 -04:00
call-lowering-const-bitcast-func.ll [GlobalISel][CallLowering] Look through bitcasts from constant function pointers. 2020-02-07 15:32:54 -08:00
call-lowering-i128-on-stack.ll [AArch64][GlobalISel] Fall back on attempts to allocate split types on the stack. 2019-09-11 23:53:23 +00:00
call-lowering-i256-crash.ll [GlobalISel] Fix a crash when handling an invalid MVT during call lowering. 2019-04-12 22:05:46 +00:00
call-translator-cse.ll [AArch64][GlobalISel] CallLowering: Don't generate new copies each time we need 2020-04-09 17:08:56 -07:00
call-translator-ios.ll [AArch64][GlobalISel] CallLowering: Don't generate new copies each time we need 2020-04-09 17:08:56 -07:00
call-translator-musttail.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
call-translator-tail-call-sret.ll OpaquePtr: Bulk update tests to use typed sret 2020-11-20 17:58:26 -05:00
call-translator-tail-call-weak.ll [AArch64] Provide Darwin variants of most calling conventions 2020-05-20 16:03:48 -07:00
call-translator-tail-call.ll OpaquePtr: Bulk update tests to use typed byval 2020-11-20 14:00:46 -05:00
call-translator-variadic-musttail.ll [AArch64][GlobalISel] Select G_ADD_LOW into a MOVaddr pseudo. 2020-06-09 16:47:58 -07:00
call-translator.ll [GlobalISel][CallLowering] Look through call parameters for flags 2020-08-18 08:48:56 -07:00
combine-anyext-crash.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
combine-copy.mir [GlobalISel] CombinerHelper: Fix a bug in matchCombineCopy 2019-12-02 12:05:09 -08:00
combine-ext-debugloc.mir [AArch64][GlobalISel] Split G_GLOBAL_VALUE into ADRP + G_ADD_LOW and optimize. 2020-06-01 16:00:56 -07:00
combine-ext.mir GlobalISel: Add combines for extend operations 2020-09-01 08:50:06 -07:00
combine-fabs.mir [GISel] Add new combines for unary FP instrs with constant operand 2020-09-16 10:34:15 -07:00
combine-fconstant.mir [AArch64PreLegalizerCombiner] Fix debug invariance issue in matchFConstantToConstant [13/14] 2020-04-22 17:03:41 -07:00
combine-flog2.mir [GISel] Add new combines for unary FP instrs with constant operand 2020-09-16 10:34:15 -07:00
combine-fneg.mir [GISel] Add new combines for unary FP instrs with constant operand 2020-09-16 10:34:15 -07:00
combine-fptrunc.mir [GISel] Add new combines for unary FP instrs with constant operand 2020-09-16 10:34:15 -07:00
combine-fsqrt.mir [GISel] Add new combines for unary FP instrs with constant operand 2020-09-16 10:34:15 -07:00
combine-insert-vec-elt.mir [GISel]: Few InsertVecElt combines 2020-10-28 12:27:07 -07:00
combine-inttoptr-ptrtoint.mir [GISel] Add combiners for G_INTTOPTR and G_PTRTOINT 2020-07-31 10:13:36 -07:00
combine-mul-to-shl.mir [GlobalISel] Add new combine to convert scalar G_MUL to G_SHL. 2020-01-29 13:39:00 -08:00
combine-mul.mir [GISel] Add new GISel combiners for G_MUL 2020-09-15 16:08:47 -07:00
combine-ptradd-int2ptr.mir [GISel] Add combine for constant G_PTR_ADD offsets. 2020-10-13 17:26:12 -07:00
combine-ptrtoint.mir [GISel] Add combiners for G_INTTOPTR and G_PTRTOINT 2020-07-31 10:13:36 -07:00
combine-select.mir [GISel] Add new GISel combiners for G_SELECT 2020-08-27 09:40:15 -07:00
combine-sext-debugloc.mir [GlobalISel] Assign the correct location when combining G_SEXT. 2020-05-12 15:32:18 -07:00
combine-sext-trunc-sextload.mir [GlobalISel] Enable copy-propagation in post-legalizer combiner. 2020-08-15 13:44:30 -07:00
combine-shl.mir GlobalISel: Combine `op undef, x` to 0 2020-09-08 09:46:38 -07:00
combine-trunc.mir GlobalISel: Fix truncating shift amount in trunc (shl) combine 2020-09-23 09:07:50 -04:00
combine-unmerge.mir [GlobalISel] Add a `X, Y = G_UNMERGE(G_ZEXT Z)` -> X = G_ZEXT Z; Y = 0 combine 2020-09-14 17:27:23 -07:00
combiner-load-store-indexing.ll [GIsel][CombinerHelper] Fix for missed ElideBrByInvertingCond/CombineIndexedLoadStore combines [4/14] 2020-04-22 17:03:40 -07:00
constant-dbg-loc.ll [GlobalISel] Remove debug locations when emitting constants. 2020-04-27 11:27:08 -07:00
constant-mir-debugify.mir [MachineDebugify] Insert synthetic DBG_VALUE instructions 2020-04-22 17:03:39 -07:00
contract-store.mir [GlobalISel][AArch64] Fix contract cross-bank copies with SIMD instructions 2020-02-05 10:38:35 -08:00
darwin-tls-call-clobber.ll Reapply "RegAllocFast: Rewrite and improve" 2020-09-30 10:35:25 -04:00
debug-cpp.ll Revert "[DebugInfo] Remove some users of DBG_VALUEs IsIndirect field" 2020-02-06 14:41:40 +00:00
debug-insts.ll [GlobalISel][test] Add REQUIRES: asserts after D76934 2020-06-11 13:50:56 -07:00
dynamic-alloca-lifetime.ll [GlobalISel] Add ISel support for @llvm.lifetime.start and @llvm.lifetime.end 2019-01-28 19:22:29 +00:00
dynamic-alloca.ll [Alignment][NFC] Convert MachineIRBuilder::buildDynStackAlloc to Align 2020-04-03 09:05:19 +00:00
fallback-nofastisel.ll
…
fconstant-dbg-loc.ll [GlobalISel] Remove debug locations when emitting G_FCONSTANT. 2020-05-11 16:25:03 -07:00
fold-brcond-fcmp.mir [GlobalISel][AArch64] Don't emit cset for G_FCMPs feeding into G_BRCONDs 2020-10-01 15:34:16 -07:00
fold-fp-select.mir [AArch64][GlobalISel] Don't use explicit zero registers for compare results. 2020-10-14 16:49:33 -07:00
fold-select.mir [AArch64][GlobalISel] Move imm adjustment for G_ICMP to post-legalizer lowering 2020-10-22 15:27:36 -07:00
fp16-copy-gpr.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
fp128-legalize-crash-pr35690.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
freeze.ll [AArch64][GlobalISel] Add legalizer & selector support for G_FREEZE. 2020-05-18 16:25:33 -07:00
gisel-abort.ll
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gisel-commandline-option-fastisel.ll Rename ExpandISelPseudo->FinalizeISel, delay register reservation 2019-06-19 00:25:39 +00:00
gisel-commandline-option.ll [AArch64][GlobalISel] Introduce a new post-isel optimization pass. 2020-10-23 10:18:36 -07:00
gisel-fail-intermediate-legalizer.ll GlobalISel: Implement widenScalar for G_SITOFP/G_UITOFP sources 2019-10-01 01:06:48 +00:00
inline-asm.ll
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inline-memcpy.mir GlobalISel: Add generic instructions for memory intrinsics 2020-08-26 20:08:45 -04:00
inline-memmove.mir GlobalISel: Add generic instructions for memory intrinsics 2020-08-26 20:08:45 -04:00
inline-memset.mir GlobalISel: Add generic instructions for memory intrinsics 2020-08-26 20:08:45 -04:00
inline-small-memcpy.mir GlobalISel: Add generic instructions for memory intrinsics 2020-08-26 20:08:45 -04:00
integration-shuffle-vector.ll [AArch64] Provide Darwin variants of most calling conventions 2020-05-20 16:03:48 -07:00
irtranslator-atomic-metadata.ll GlobalISel: Apply target MMO flags to atomics 2020-01-16 13:49:43 -05:00
irtranslator-bitcast.ll
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irtranslator-block-order.ll
…
irtranslator-condbr-lower-tree.ll [GlobalISel] Enable usage of BranchProbabilityInfo in IRTranslator. 2020-09-09 14:31:12 -07:00
irtranslator-convert-fp16-intrinsics.ll GlobalISel: Translate llvm.convert.{to|from}.fp16 intrinsics 2020-07-28 11:46:05 -04:00
irtranslator-dilocation.ll
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irtranslator-duplicate-types-param.ll
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irtranslator-exceptions.ll [GlobalISel][IRTranslator] Support PHI instructions in landingpad blocks 2020-08-20 10:49:31 +02:00
irtranslator-extends.ll [globalisel] Add G_SEXT_INREG 2019-08-09 21:11:20 +00:00
irtranslator-fixed-point-intrinsics.ll GlobalISel: Define mulfix/divfix opcodes 2020-07-24 20:02:20 -04:00
irtranslator-fp-min-max-intrinsics.ll GlobalISel: Define the full family of FP min/max instructions 2019-07-10 16:31:15 +00:00
irtranslator-indirect-br-repeated-block.ll [GlobalISel] Don't add duplicate successors to MBBs when translating indirectbr 2020-05-08 13:40:02 -07:00
irtranslator-inline-asm.ll [GlobalISel][InlineAsm] Fix matching input constraint to physreg 2020-08-06 14:35:51 +02:00
irtranslator-load-metadata.ll GlobalISel: Preserve load/store metadata in IRTranslator 2020-01-16 13:49:43 -05:00
irtranslator-localescape.ll GlobalISel: Handle llvm.localescape 2020-08-04 15:19:02 -04:00
irtranslator-max-address-space.ll GlobalISel: Fix address space limit in LLT 2019-01-26 01:42:13 +00:00
irtranslator-memfunc-undef.ll [GlobalISel] Translate memset/memmove/memcpy from undef ptrs into nops 2019-06-10 21:53:56 +00:00
irtranslator-no-op-intrinsics.ll Try to fix buildbots after d3205bbca3 2020-10-26 11:49:21 +01:00
irtranslator-reductions.ll [GlobalISel] Add translation support for vector reduction intrinsics. 2020-10-16 10:17:53 -07:00
irtranslator-split-vector-arg.ll [GISel][CallLowering] Enable vector support in argument lowering 2019-10-11 20:22:57 +00:00
irtranslator-stack-evt-bug47619.ll AArch64/GlobalISel: Narrow stack passed argument access size 2020-09-25 13:35:17 -04:00
irtranslator-stackprotect-check.ll GlobalISel: Preserve load/store metadata in IRTranslator 2020-01-16 13:49:43 -05:00
irtranslator-store-metadata.ll GlobalISel: Preserve load/store metadata in IRTranslator 2020-01-16 13:49:43 -05:00
irtranslator-switch-bittest.ll [GlobalISel] Enable usage of BranchProbabilityInfo in IRTranslator. 2020-09-09 14:31:12 -07:00
irtranslator-tbaa.ll Revert "[GISel]: Fix incorrect IRTranslation while translating null pointer types" 2020-03-30 19:30:42 -04:00
irtranslator-volatile-load-pr36018.ll
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irtranslator-weird-alloca-size.ll [IRTranslator] Use the alloc size instead of the store size when translating allocas 2019-05-03 01:23:56 +00:00
labels-are-not-dead.mir GlobalISel: Handle llvm.localescape 2020-08-04 15:19:02 -04:00
legalize-abs.mir [GlobalISel] Add lowering support for G_ABS and use for AArch64. 2020-09-18 16:17:18 -07:00
legalize-add.mir [AArch64][GlobalISel] Make <8 x s8> integer arithmetic ops legal. 2020-10-01 14:35:21 -07:00
legalize-and.mir
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legalize-atomicrmw.mir [AArch64][GlobalISel] Make s8 and s16 G_CONSTANTs legal. 2019-06-21 16:43:50 +00:00
legalize-blockaddress.mir [MachineVerifier][GlobalISel] Check that branches have a MBB operand or are declared indirect. Add missing properties to G_BRJT, G_BRINDIRECT 2020-06-15 11:17:09 +02:00
legalize-bswap.mir [AArch64][GlobalISel] Tweak legalization rule for G_BSWAP to handle widening s16. 2019-09-25 04:52:42 +00:00
legalize-build-vector.mir [AArch64][GlobalISel] Make <8 x s8> of G_BUILD_VECTOR legal. 2020-09-18 10:32:33 -07:00
legalize-ceil.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
legalize-cmp.mir GlobalISel: Allow CSE of G_IMPLICIT_DEF 2020-02-05 17:47:21 -05:00
legalize-cmpxchg-with-success.mir
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legalize-cmpxchg.mir [AArch64][GlobalISel] Make s8 and s16 G_CONSTANTs legal. 2019-06-21 16:43:50 +00:00
legalize-combines.mir GlobalISel: Combine g_extract with g_merge_values 2019-02-04 23:41:59 +00:00
legalize-concat-vectors.mir [AArch64][GlobalISel] Add some support for G_CONCAT_VECTORS. 2019-03-14 22:48:15 +00:00
legalize-constant.mir [AArch64][GlobalISel] Split G_GLOBAL_VALUE into ADRP + G_ADD_LOW and optimize. 2020-06-01 16:00:56 -07:00
legalize-cos.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
legalize-div.mir [AArch64][GlobalISel] Make G_SEXT_INREG legal and add selection support. 2020-06-19 13:20:41 -07:00
legalize-dyn-alloca.mir [update_mir_test_checks] Handle MI flags properly 2019-10-14 22:01:58 +00:00
legalize-exceptions.ll
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legalize-exp.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
legalize-ext-cse.mir [GISel]: Change how CSE is enabled by default for each pass 2019-01-24 23:11:25 +00:00
legalize-ext-csedebug-output.mir [GlobalISel] Regex the opcodes in unit test to fix non-deterministic ordering 2019-02-10 19:53:43 +00:00
legalize-ext.mir [AArch64][GlobalISel] Make G_SEXT_INREG legal and add selection support. 2020-06-19 13:20:41 -07:00
legalize-extload.mir [AArch64][GlobalISel] Make extloads to i64 legal. 2019-06-04 21:51:34 +00:00
legalize-extract-vector-elt.mir [AArch64][GlobalISel] Make G_EXTRACT_VECTOR_ELT of <2 x p0> legal. 2020-11-20 14:07:45 -08:00
legalize-extracts.mir [AArch64][GlobalISel] Add support for s128 loads, stores, extracts, truncs. 2019-07-23 22:05:13 +00:00
legalize-fcmp.mir
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legalize-fexp2.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
legalize-fma.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
legalize-fp-arith.mir [AArch64][GlobalISel] Clamp oversize FP arithmetic vectors. 2020-09-30 18:03:37 -07:00
legalize-fp16-fconstant.mir [AArch64][GlobalISel] Mark G_FCONSTANT as legal when there is full fp16 support 2020-11-11 13:25:11 -08:00
legalize-fpext.mir [AArch64][GlobalISel] Camp oversize v4s64 G_FPEXT operations. 2020-10-01 13:08:31 -07:00
legalize-fptoi.mir [AArch64][GlobalISel] Add some vector support for fp <-> int conversions. 2019-01-28 02:27:59 +00:00
legalize-fptrunc.mir [AArch64][GlobalISel] Fix bug in fewVectorElts action while legalizing oversize G_FPTRUNC vectors. 2020-09-17 08:56:26 -07:00
legalize-freeze.mir [AArch64][GlobalISel] Add some more legal types for G_PHI, G_IMPLICIT_DEF, G_FREEZE. 2020-09-30 17:25:33 -07:00
legalize-frint.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
legalize-global.mir [AArch64][GlobalISel] Split G_GLOBAL_VALUE into ADRP + G_ADD_LOW and optimize. 2020-06-01 16:00:56 -07:00
legalize-ignore-non-generic.mir
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legalize-insert-vector-elt.mir [AArch64][GlobalISel] Make <8 x s16> for G_INSERT_VECTOR_ELT legal. 2020-09-25 01:59:16 -07:00
legalize-inserts.mir [AArch64][GlobalISel] Add support for s128 loads, stores, extracts, truncs. 2019-07-23 22:05:13 +00:00
legalize-intrinsic-round.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
legalize-intrinsic-trunc.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
legalize-inttoptr-xfail-1.mir Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
legalize-inttoptr-xfail-2.mir Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
legalize-itofp.mir GlobalISel: Handle arbitrary FewerElementsVector for G_IMPLICIT_DEF 2020-08-03 09:14:08 -04:00
legalize-load-store-fewerElts.mir [AArch64][GlobalISel] Flesh out vector load/store support for more types. 2019-04-11 20:40:01 +00:00
legalize-load-store-vector-of-ptr-debugloc.mir [AArch64][GlobalISel] Add more specific debug info tests for 613f12dd8e. 2020-07-09 17:13:16 -07:00
legalize-load-store-vector-of-ptr.mir [AArch64][GlobalISel] Set the current debug loc when missing in some cases. 2020-04-23 01:34:57 -07:00
legalize-load-store.mir [AArch64][GlobalISel] Make G_STORE <8 x s8> legal. 2020-09-17 16:42:18 -07:00
legalize-load-trunc.mir [GlobalISel] combine trunc(trunc) pattern 2020-04-08 11:58:28 +02:00
legalize-log.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
legalize-log2.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
legalize-log10.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
legalize-lrint.mir [AArch64][GlobalISel] Add legalization & selection support for G_INTRINSIC_LRINT. 2020-07-30 16:14:56 -07:00
legalize-memcpy-et-al.mir GlobalISel: Add generic instructions for memory intrinsics 2020-08-26 20:08:45 -04:00
legalize-memcpy-with-debug-info.mir GlobalISel: Add generic instructions for memory intrinsics 2020-08-26 20:08:45 -04:00
legalize-memlib-debug-loc.mir GlobalISel: Add generic instructions for memory intrinsics 2020-08-26 20:08:45 -04:00
legalize-merge-values.mir [AArch64][GlobalISel] Promote scalar G_SHL constant shift amounts to s64. 2020-09-27 01:53:26 -07:00
legalize-mul.mir [GlobalISel] Fix multiply with overflow intrinsics legalization generating invalid MIR. 2020-09-29 18:40:58 -07:00
legalize-nearbyint.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
legalize-non-pow2-load-store.mir [AArch64][GlobalISel] Promote scalar G_SHL constant shift amounts to s64. 2020-09-27 01:53:26 -07:00
legalize-or.mir
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legalize-phi-insertpt-decrement.mir [MachineDebugify] Insert synthetic DBG_VALUE instructions 2020-04-22 17:03:39 -07:00
legalize-phi.mir [AArch64][GlobalISel] Add some more legal types for G_PHI, G_IMPLICIT_DEF, G_FREEZE. 2020-09-30 17:25:33 -07:00
legalize-pow.mir [AArch64] Fix GlobalISel tests on non-darwin platforms 2020-05-20 16:26:58 -07:00
legalize-property.mir
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legalize-ptr-add.mir [AArch64][GlobalISel] Make G_SEXT_INREG legal and add selection support. 2020-06-19 13:20:41 -07:00
legalize-reduce-add.mir [AArch64][GlobalISel] Add basic legalizer rules for supported add/fadd reductions. 2020-10-16 10:35:46 -07:00
legalize-reduce-fadd.mir [AArch64][GlobalISel] Add basic legalizer rules for supported add/fadd reductions. 2020-10-16 10:35:46 -07:00
legalize-rem.mir [AArch64][GlobalISel] Make G_SEXT_INREG legal and add selection support. 2020-06-19 13:20:41 -07:00
legalize-s128-div.mir [AArch64] Provide Darwin variants of most calling conventions 2020-05-20 16:03:48 -07:00
legalize-select.mir [GlobalISel] Add support for lowering of vector G_SELECT and use for AArch64. 2020-09-28 14:00:46 -07:00
legalize-sext-128.ll [GlobalISel][NFC] Regression test cases for aarch64 legalizer (s128 sext+icmp). 2019-09-01 00:45:28 +00:00
legalize-sext-128.mir [GlobalISel][NFC] Regression test cases for aarch64 legalizer (s128 sext+icmp). 2019-09-01 00:45:28 +00:00
legalize-sext-copy.mir
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legalize-sext-zext-128.mir [GlobalISel] Enable artifact combiner to combine starting from a G_MERGE_VALUES. 2020-04-15 10:34:13 -07:00
legalize-sext.mir [AArch64][GlobalISel] Make G_SEXT_INREG legal and add selection support. 2020-06-19 13:20:41 -07:00
legalize-sextload.mir
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legalize-shift-imm-promote-dloc.mir [AArch64][GlobalISel] Add more specific debug info tests for 613f12dd8e. 2020-07-09 17:13:16 -07:00
legalize-shift.mir [AArch64][GlobalISel] Make <8 x s8> shifts legal and add selection support. 2020-10-01 14:21:18 -07:00
legalize-shuffle-vector.mir [AArch64][GlobalISel] Make <2 x p0> of G_SHUFFLE_VECTOR legal. 2020-11-23 22:59:35 -08:00
legalize-simple.mir GlobalISel: Verify G_BITCAST changes the type 2020-07-08 17:16:27 -04:00
legalize-sin.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
legalize-sqrt.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
legalize-sub.mir
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legalize-undef.mir GlobalISel: Handle arbitrary FewerElementsVector for G_IMPLICIT_DEF 2020-08-03 09:14:08 -04:00
legalize-unmerge-values.mir [AArch64][GlobalISel] Use the look-through constant helper for the shift s32->s64 custom legalization. 2020-09-27 01:25:03 -07:00
legalize-vaarg.mir [AArch64][GlobalISel] Add more specific debug info tests for 613f12dd8e. 2020-07-09 17:13:16 -07:00
legalize-vector-cmp.mir [AArch64][GlobalISel] Alias rules for G_FCMP to G_ICMP. 2020-10-01 15:20:09 -07:00
legalize-vector-shift.mir [AArch64][GlobalISel] Make <4 x s32> G_ASHR and G_LSHR legal. 2019-09-21 09:21:10 +00:00
legalize-xor.mir
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legalize-zextload.mir
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legalizer-combiner-zext-trunc-crash.mir [Legalizer] Making artifact combining order-independent 2019-12-13 15:45:18 -08:00
legalizer-combiner.mir [GlobalISel] Enable artifact combiner to combine starting from a G_MERGE_VALUES. 2020-04-15 10:34:13 -07:00
legalizer-info-validation.mir [AArch64][GlobalISel] Mark G_FCONSTANT as legal when there is full fp16 support 2020-11-11 13:25:11 -08:00
load-addressing-modes.mir [AArch64][GlobalISel] Don't reconvert to p0 in convertPtrAddToAdd(). 2020-02-03 11:50:22 -08:00
load-wro-addressing-modes.mir [AArch64][GlobalISel] Look through a G_ZEXT when trying to match shift-extended register offsets. 2020-11-16 10:50:46 -08:00
localizer-arm64-tti.ll [AArch64][GlobalISel] Don't localize TLS G_GLOBAL_VALUEs on Darwin. 2020-03-24 13:35:50 -07:00
localizer-in-O0-pipeline.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
localizer.mir [AArch64][GlobalISel] Split G_GLOBAL_VALUE into ADRP + G_ADD_LOW and optimize. 2020-06-01 16:00:56 -07:00
machine-cse-mid-pipeline.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
memcpy_chk_no_tail.ll Add an operand to memory intrinsics to denote the "tail" marker. 2019-09-28 05:33:21 +00:00
no-neon-no-fp.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
no-regclass.mir
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non-pow-2-extload-combine.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
observer-change-crash.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
opt-and-tbnz-tbz.mir [AArch64][GlobalISel] Don't use explicit zero registers for compare results. 2020-10-14 16:49:33 -07:00
opt-fold-and-tbz-tbnz.mir [AArch64][GlobalISel] Avoid copies to target register bank for subregister copies 2020-03-05 11:13:02 -08:00
opt-fold-compare.mir [AArch64][GlobalISel] Select CSINC and CSINV for G_SELECT with constants 2020-11-12 14:44:01 -08:00
opt-fold-ext-tbz-tbnz.mir [AArch64][GlobalISel] Avoid copies to target register bank for subregister copies 2020-03-05 11:13:02 -08:00
opt-fold-shift-tbz-tbnz.mir [AArch64][GlobalISel] Avoid copies to target register bank for subregister copies 2020-03-05 11:13:02 -08:00
opt-fold-trunc-tbz-tbnz.mir [AArch64][GlobalISel] Walk through G_TRUNC in getTestBitReg 2020-01-31 11:09:55 -08:00
opt-fold-xor-tbz-tbnz.mir [AArch64][GlobalISel] Fold G_XOR into TB(N)Z bit calculation 2020-02-03 15:22:24 -08:00
opt-shifted-reg-compare.mir [AArch64][GlobalISel] Don't use explicit zero registers for compare results. 2020-10-14 16:49:33 -07:00
phi-mir-debugify.mir [MachineDebugify] Insert synthetic DBG_VALUE instructions 2020-04-22 17:03:39 -07:00
postlegalizer-combiner-and-trivial-mask.mir AArch64/GlobalISel: Fix missing function begin marker in test 2020-08-27 16:56:17 -04:00
postlegalizer-combiner-copy-prop.mir [GlobalISel] Enable copy-propagation in post-legalizer combiner. 2020-08-15 13:44:30 -07:00
postlegalizer-combiner-store-undef.mir [AArch64][GlobalISel] Add a post-legalizer combiner with a very simple combine. 2020-05-21 18:47:32 -07:00
postlegalizer-lowering-adjust-icmp-imm.mir [AArch64][GlobalISel] Move imm adjustment for G_ICMP to post-legalizer lowering 2020-10-22 15:27:36 -07:00
postlegalizer-lowering-ext.mir [AArch64][GlobalISel] Split post-legalizer combiner to allow for lowering at -O0 2020-10-22 14:43:25 -07:00
postlegalizer-lowering-rev.mir [AArch64][GlobalISel] Split post-legalizer combiner to allow for lowering at -O0 2020-10-22 14:43:25 -07:00
postlegalizer-lowering-shuffle-duplane.mir [AArch64][GlobalISel] Add AArch64::G_DUPLANE[X] opcodes for lane duplicates. 2020-11-05 11:18:11 -08:00
postlegalizer-lowering-shuffle-splat.mir [AArch64][GlobalISel] Split post-legalizer combiner to allow for lowering at -O0 2020-10-22 14:43:25 -07:00
postlegalizer-lowering-trn.mir [AArch64][GlobalISel] Split post-legalizer combiner to allow for lowering at -O0 2020-10-22 14:43:25 -07:00
postlegalizer-lowering-uzp.mir [AArch64][GlobalISel] Split post-legalizer combiner to allow for lowering at -O0 2020-10-22 14:43:25 -07:00
postlegalizer-lowering-vashr-vlshr.mir [AArch64][GlobalISel] Split post-legalizer combiner to allow for lowering at -O0 2020-10-22 14:43:25 -07:00
postlegalizer-lowering-zip.mir [AArch64][GlobalISel] Split post-legalizer combiner to allow for lowering at -O0 2020-10-22 14:43:25 -07:00
postlegalizercombiner-extending-loads.mir [AArch64][GlobalISel] Enable extending loads combines post-legalization. 2020-05-28 22:48:20 -07:00
postlegalizercombiner-extractvec-faddp.mir [AArch64][GlobalISel] Add combine for G_EXTRACT_VECTOR_ELT to allow selection of pairwise FADD. 2020-11-03 17:25:14 -08:00
postlegalizercombiner-hoist-same-hands.mir [GlobalISel] Combine (logic_op (op x...), (op y...)) -> (op (logic_op x, y)) 2020-08-11 10:40:06 -07:00
postselectopt-dead-cc-defs-in-fcmp.mir [AArch64][GlobalISel] Introduce a new post-isel optimization pass. 2020-10-23 10:18:36 -07:00
prelegalizercombiner-ashr-shl-to-sext-inreg.mir [GlobalISel] Add a combine for ashr(shl x, c), c --> sext_inreg x, c' 2020-08-18 10:42:15 -07:00
prelegalizercombiner-binop-same-val.mir [GlobalISel] Implement identity transforms for x op x -> x 2020-03-30 18:22:37 -07:00
prelegalizercombiner-br.mir Add REQUIRES: asserts to a test that uses an asserts only flag. 2020-09-09 14:31:12 -07:00
prelegalizercombiner-concat-vectors.mir [GISel]: Few InsertVecElt combines 2020-10-28 12:27:07 -07:00
prelegalizercombiner-copy-prop-disabled.mir [gicombiner] Allow disable-rule option to disable all-except-... 2020-06-16 16:57:16 -07:00
prelegalizercombiner-extending-loads-cornercases.mir Add -debugify-and-strip-all to add debug info before a pass and remove it after 2020-04-10 16:36:07 -07:00
prelegalizercombiner-extending-loads-s1.mir GlobalISel: Add combines for extend operations 2020-09-01 08:50:06 -07:00
prelegalizercombiner-extending-loads.mir [globalisel] Fix iterator invalidation in the extload combines 2019-06-17 20:56:31 +00:00
prelegalizercombiner-hoist-same-hands.mir [GlobalISel] Combine (logic_op (op x...), (op y...)) -> (op (logic_op x, y)) 2020-08-11 10:40:06 -07:00
prelegalizercombiner-invert-cmp.mir [GlobalISel] Extend not_cmp_fold to work on conditional expressions 2020-09-07 09:31:08 +01:00
prelegalizercombiner-not-really-equiv-insts.mir [GlobalISel] Don't combine instructions which are fed by memory instructions. 2020-05-27 12:48:58 -07:00
prelegalizercombiner-ptradd-chain.mir [AArch64][GlobalISel] Fold a chain of two G_PTR_ADDs of constant offsets. 2020-01-07 14:12:42 -08:00
prelegalizercombiner-select.mir [GlobalISel] Fix equality for copies from physregs in matchEqualDefs 2020-03-27 17:52:21 -07:00
prelegalizercombiner-sextload-from-sextinreg.mir [GlobalISel] Add a combine for sext_inreg(load x), c --> sextload x 2020-08-18 10:42:15 -07:00
prelegalizercombiner-shuffle-vector.mir [GlobalISel] Change representation of shuffle masks in MachineOperand. 2020-01-13 16:55:41 -08:00
prelegalizercombiner-simplify-add.mir [GlobalISel] Simplify G_ADD when it has (0-X) on the LHS or RHS 2020-06-15 09:43:24 -07:00
prelegalizercombiner-trivial-arith.mir [GlobalISel] Look through extends etc in CombinerHelper::matchConstantOp 2020-06-15 16:34:25 -07:00
prelegalizercombiner-undef.mir [GlobalISel] Port some basic shufflevector undef combines from the DAGCombiner 2020-03-19 16:46:06 -07:00
prelegalizercombiner-xor-of-and-with-same-reg.mir [GlobalISel] Combine (xor (and x, y), y) -> (and (not x), y) 2020-09-28 10:08:14 -07:00
preselect-process-phis.mir [AArch64][GlobalISel] Don't use explicit zero registers for compare results. 2020-10-14 16:49:33 -07:00
reg-bank-128bit.mir
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regbank-ceil.ll
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regbank-dup.mir [AArch64][GlobalISel] Move dup optimization into post-legalizer combiner 2020-06-05 17:46:28 -07:00
regbank-extract-vector-elt.mir [AArch64][GlobalISel] Widen G_EXTRACT_VECTOR_ELT element types if < 8b. 2020-09-17 11:50:33 -07:00
regbank-extract.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
regbank-fma.mir [update_mir_test_checks] Handle MI flags properly 2019-10-14 22:01:58 +00:00
regbank-fp-use-def.mir [AArch64][GlobalISel] Infer whether G_PHI is going to be a FPR in regbankselect 2020-09-28 10:37:09 -07:00
regbank-inlineasm.mir [GlobalISel][InlineAsm] Add support for basic output operand constraints 2020-05-06 10:06:13 +02:00
regbank-insert-vector-elt.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
regbank-intrinsic-round.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
regbank-intrinsic-trunc.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
regbank-nearbyint.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
regbank-select.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
regbank-shift-imm-64.mir [AArch64][GlobalISel] Overhaul legalization & isel or shifts to select immediate forms. 2019-07-03 01:49:06 +00:00
regbank-trunc-s128.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
regbankselect-build-vector.mir [AArch64][GlobalISel] If a G_BUILD_VECTOR operands are all G_CONSTANT then assign to gpr bank. 2020-09-25 18:27:57 -07:00
regbankselect-dbg-value.mir
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regbankselect-default.mir [AArch64][GlobalISel] Handle rtcGPR64RegClassID in AArch64RegisterBankInfo::getRegBankFromRegClass() 2020-08-19 12:52:30 -07:00
regbankselect-reductions.mir [AArch64][GlobalISel] Regbankselect reductions to use FPR bank for scalars. 2020-10-16 10:42:15 -07:00
regbankselect-reg_sequence.mir GlobalISel: Fix RegBankSelect for REG_SEQUENCE 2019-03-21 20:45:36 +00:00
regbankselect-unmerge-vec.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
ret-1x-vec.ll [GlobalISel] Handle <1 x T> vector return types properly. 2019-05-06 19:41:01 +00:00
ret-vec-promote.ll [GlobalISel][AArch64] Allow CallLowering to handle types which are normally 2019-04-09 21:22:33 +00:00
retry-artifact-combine.mir [Legalizer] Making artifact combining order-independent 2019-12-13 15:45:18 -08:00
select-arith-extended-reg.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
select-arith-shifted-reg.mir [AArch64][GlobalISel] Select patterns which use shifted register operands 2019-08-20 22:18:06 +00:00
select-atomic-load-store.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
select-atomicrmw.mir [GlobalISel] Import patterns containing SUBREG_TO_REG 2019-08-28 20:12:31 +00:00
select-binop.mir [AArch64][GlobalISel] Add tests for pre-existing selection support for <4 x s16> arithmetic/bitwise ops. 2020-09-18 17:13:55 -07:00
select-bitcast-bigendian.mir
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select-bitcast.mir GlobalISel: Verify G_BITCAST changes the type 2020-07-08 17:16:27 -04:00
select-blockaddress.mir [MachineVerifier][GlobalISel] Check that branches have a MBB operand or are declared indirect. Add missing properties to G_BRJT, G_BRINDIRECT 2020-06-15 11:17:09 +02:00
select-br.mir
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select-brcond-of-binop.mir [AArch64][GlobalISel] Use emitTestBit in selection for G_BRCOND 2020-10-01 15:33:34 -07:00
select-bswap.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
select-build-vector.mir [AArch64][GlobalISel] Select all-zero G_BUILD_VECTOR into a zero mov. 2020-09-30 23:53:38 -07:00
select-cbz.mir [AArch64][GlobalISel] Move imm adjustment for G_ICMP to post-legalizer lowering 2020-10-22 15:27:36 -07:00
select-ceil.mir [GlobalISel][AArch64] Add isel support for FP16 vector @llvm.ceil 2019-01-24 22:00:41 +00:00
select-cmp.mir [AArch64][GlobalISel] Select arith extended add/sub in manual selection code 2020-11-11 09:26:03 -08:00
select-cmpxchg.mir [GlobalISel] Import patterns containing SUBREG_TO_REG 2019-08-28 20:12:31 +00:00
select-concat-vectors.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
select-const-vector.mir [AArch64][GlobalISel] Improve codegen for some constant vectors by using constant pool loads. 2020-06-23 19:23:47 -07:00
select-constant.mir [GlobalISel] Rewrite the elide-br-by-swapping-icmp-ops combine to do less. 2020-09-09 13:08:16 -07:00
select-ctlz.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
select-dbg-value.mir
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select-dup.mir [AArch64][GlobalISel] Add pre-isel lowering to convert p0 G_DUPs to use s64. 2020-11-23 22:59:35 -08:00
select-ext.mir [AArch64][GlobalISel] Add G_EXT and select ext using it 2020-06-15 12:20:59 -07:00
select-extload.mir
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select-extract-vector-elt.mir [AArch64][GlobalISel] Make G_EXTRACT_VECTOR_ELT of <2 x p0> legal. 2020-11-20 14:07:45 -08:00
select-extract.mir [AArch64][GlobalISel] Add support for s128 loads, stores, extracts, truncs. 2019-07-23 22:05:13 +00:00
select-fabs.mir [GlobalISel][AArch64] Select G_FABS 2019-01-30 22:54:21 +00:00
select-faddp.mir [AArch64][GlobalISel] Add combine for G_EXTRACT_VECTOR_ELT to allow selection of pairwise FADD. 2020-11-03 17:25:14 -08:00
select-fcmp.mir [AArch64][GlobalISel] NFC: Refactor G_FCMP selection code 2020-09-30 16:50:39 -07:00
select-floor.mir [GlobalISel][AArch64] Select G_FFLOOR 2019-02-11 17:22:58 +00:00
select-fma.mir
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select-fp-casts.mir [AArch64][GlobalISel] Add isel support for a couple vector exts/truncs 2019-02-11 18:56:39 +00:00
select-fp16-fconstant.mir [AArch64][GlobalISel] Mark G_FCONSTANT as legal when there is full fp16 support 2020-11-11 13:25:11 -08:00
select-frameaddr.ll Revert "Revert rG6078f2fedcac5797ac39ee5ef3fd7a35ef1202d5 - "[AArch64][GlobalISel]: Support @llvm.{return,frame}address selection."" 2020-01-15 10:13:11 -08:00
select-frint-nofp16.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
select-frint.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
select-gv-cmodel-large.mir Describe stack-id as an enum 2019-06-17 09:13:29 +00:00
select-gv-cmodel-tiny.mir Describe stack-id as an enum 2019-06-17 09:13:29 +00:00
select-imm.mir [AArch64][GlobalISel] Emit constant pool loads for 64 bit fp immediates. 2020-06-15 20:53:09 -07:00
select-implicit-def.mir
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select-insert-extract.mir
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select-insert-vector-elt.mir Revert "Revert "[AArch64][GlobalISel] Add selection support for <8 x s16> G_INSERT_VECTOR_ELT with GPR scalar."" 2020-09-28 13:44:51 -07:00
select-int-ext.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
select-int-ptr-casts.mir
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select-intrinsic-aarch64-hint.mir
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select-intrinsic-aarch64-sdiv.mir
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select-intrinsic-crypto-aesmc.mir
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select-intrinsic-round.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
select-intrinsic-trunc.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
select-jump-table-brjt-constrain.mir [AArch64][GlobalISel] Don't use explicit zero registers for compare results. 2020-10-14 16:49:33 -07:00
select-jump-table-brjt.mir [AArch64][GlobalISel] Don't use explicit zero registers for compare results. 2020-10-14 16:49:33 -07:00
select-ldaxr-intrin.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
select-ldxr-intrin.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
select-load-store-vector-of-ptr.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
select-load.mir [globalisel] Rename G_GEP to G_PTR_ADD 2019-11-05 10:31:17 -08:00
select-logical-imm.mir [AArch64][GlobalISel] Select logical_imm32 and logical_imm64 patterns 2019-08-20 22:31:25 +00:00
select-logical-shifted-reg.mir [AArch64][GlobalISel] Select patterns which use shifted register operands 2019-08-20 22:18:06 +00:00
select-mul.mir
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select-muladd.mir
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select-nearbyint.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
select-neon-vcvtfxu2fp.mir
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select-phi.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
select-pr32733.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
select-property.mir
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select-ptr-add.mir [AArch64][GlobalISel] Optimize G_PTR_ADD with a negated offset to be a G_SUB. 2020-11-11 22:46:53 -08:00
select-reduce-add.mir [AArch64][GlobalISel] Add selection support for v2s32 and v2s64 reductions for FADD/ADD. 2020-10-16 11:41:57 -07:00
select-reduce-fadd.mir [AArch64][GlobalISel] Add selection support for v2s32 and v2s64 reductions for FADD/ADD. 2020-10-16 11:41:57 -07:00
select-redundant-zext-of-load.mir [AArch64][GlobalISel] Eliminate redundant G_ZEXT when the source is implicitly zext-loaded. 2019-08-02 21:15:36 +00:00
select-redundant-zext.mir GlobalISel: Verify G_BITCAST changes the type 2020-07-08 17:16:27 -04:00
select-returnaddr.ll [AArch64][GlobalISel] Implement __builtin_return_address for PAC-RET 2020-09-24 18:04:37 +01:00
select-returnaddress-liveins.mir [AArch64][GlobalISel] Implement __builtin_return_address for PAC-RET 2020-09-24 18:04:37 +01:00
select-rev.mir [AArch64][GlobalISel] Set hasSideEffects = 0 on custom shuffle opcodes 2020-06-12 09:39:46 -07:00
select-scalar-merge.mir
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select-scalar-shift-imm.mir [GlobalISel] Import patterns containing SUBREG_TO_REG 2019-08-28 20:12:31 +00:00
select-select.mir [AArch64][GlobalISel] Fold G_XOR x, -1 into G_SELECT and select CSINV 2020-11-16 14:14:14 -08:00
select-sextload.mir
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select-shuffle-vector.mir [AArch64][GlobalISel] Selection support for vector DUP[X]lane instructions. 2020-07-29 11:41:37 -07:00
select-shufflevec-undef-mask-elt.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
select-sqrt.mir [GlobalISel][AArch64] Add instruction selection support for @llvm.sqrt 2019-01-30 21:03:52 +00:00
select-stlxr-intrin.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
select-store.mir [AArch64][GlobalISel] Share address mode selection code for memops 2020-09-09 15:14:46 -07:00
select-stx.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
select-trap.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
select-trn.mir [AArch64][GlobalISel] Set hasSideEffects = 0 on custom shuffle opcodes 2020-06-12 09:39:46 -07:00
select-trunc.mir [AArch64][GlobalISel] Add support for s128 loads, stores, extracts, truncs. 2019-07-23 22:05:13 +00:00
select-uaddo.mir [AArch64][GlobalISel] Select arith extended add/sub in manual selection code 2020-11-11 09:26:03 -08:00
select-unmerge.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
select-uzp.mir [AArch64][GlobalISel] Select uzp1 and uzp2 2020-06-03 15:09:41 -07:00
select-vector-icmp.mir [AArch64][GlobalISel] Improve codegen for some constant vectors by using constant pool loads. 2020-06-23 19:23:47 -07:00
select-vector-shift.mir [AArch64][GlobalISel] Add a few more vector type combinations for shift selection. 2020-09-25 17:35:10 -07:00
select-with-no-legality-check.mir [SelectionDAG][ARM][AArch64][Hexagon][RISCV][X86] Add SDNPCommutative to fma and fmad nodes in tablegen. Remove explicit commuted patterns from targets. 2020-11-23 10:09:20 -08:00
select-xor.mir [AArch64][GlobalISel] Don't emit a branch for a fallthrough G_BR at -O0. 2020-09-10 15:01:26 -07:00
select-zextload.mir [AArch64][GlobalISel] Eliminate redundant G_ZEXT when the source is implicitly zext-loaded. 2019-08-02 21:15:36 +00:00
select-zip.mir [AArch64][GlobalISel] Select zip1 and zip2 2020-06-02 18:57:11 -07:00
select.mir [AArch64][GlobalISel] Don't use explicit zero registers for compare results. 2020-10-14 16:49:33 -07:00
sext-inreg-ldrow-16b.mir [AArch64][GlobalISel] Fix extended shift addressing mode selection not handling sxth. 2020-06-25 17:24:32 -07:00
store-addressing-modes.mir [globalisel] Rename G_GEP to G_PTR_ADD 2019-11-05 10:31:17 -08:00
store-wro-addressing-modes.mir [GlobalISel][AArch64] Import + select LDR*roW and STR*roW patterns 2020-01-09 12:15:56 -08:00
subreg-copy.mir [AArch64][GlobalISel] Avoid copies to target register bank for subregister copies 2020-03-05 11:13:02 -08:00
swifterror.ll OpaquePtr: Bulk update tests to use typed sret 2020-11-20 17:58:26 -05:00
swiftself.ll OpaquePtr: Update more tests to use typed sret 2020-11-20 20:08:43 -05:00
tail-call-no-save-fp-lr.ll llc: Don't overwrite frame-pointer attribute 2020-01-15 20:56:46 -05:00
tbnz-slt.mir [AArch64][GlobalISel] Don't use explicit zero registers for compare results. 2020-10-14 16:49:33 -07:00
tbz-sgt.mir [AArch64][GlobalISel] Select negative arithmetic immediates in manual selector 2020-11-11 09:20:05 -08:00
translate-constant-dag.ll Revert "Revert "[GlobalISel][Localizer] Enable intra-block localization of already-local uses."" 2020-03-06 21:35:08 -08:00
translate-gep.ll Revert "[GISel]: Fix incorrect IRTranslation while translating null pointer types" 2020-03-30 19:30:42 -04:00
unknown-intrinsic.ll
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varargs-ios-translator.ll GlobalISel: Fix creating MMOs with align 0 2019-01-31 01:38:47 +00:00
vastart.ll GlobalISel: Fix creating MMOs with align 0 2019-01-31 01:38:47 +00:00
vec-s16-param.ll [GlobalISel][AArch64] Allow CallLowering to handle types which are normally 2019-04-09 21:22:33 +00:00
widen-narrow-tbz-tbnz.mir [AArch64][GlobalISel] Use emitTestBit in selection for G_BRCOND 2020-10-01 15:33:34 -07:00
xro-addressing-mode-constant.mir [AArch64][GlobalISel] Select XRO addressing mode with wide immediates 2020-07-29 11:02:10 -07:00