llvm-project/llvm/test/CodeGen
Dmitri Gribenko 234a5297aa Add 'asserts' requiremnt to test/CodeGen/ARM/cortex-a57-misched-mla.mir
'-debug-only=machine-scheduler' only works when asserts are enabled.
2020-11-30 15:19:27 +01:00
..
AArch64 [AArch64] Regenerate min/max tests and add vXi64 umin/umax test coverage 2020-11-26 15:33:39 +00:00
AMDGPU [ConstantFold] Fold more operations to poison 2020-11-29 21:19:48 +09:00
ARC
ARM Add 'asserts' requiremnt to test/CodeGen/ARM/cortex-a57-misched-mla.mir 2020-11-30 15:19:27 +01:00
AVR [AVR] Optimize the 16-bit NEGW pseudo instruction 2020-11-17 17:51:58 +08:00
BPF [BPF][NewPM] Port bpf-adjust-opt to NPM and add it to pipeline 2020-11-26 10:11:26 -08:00
Generic OpaquePtr: Bulk update tests to use typed byval 2020-11-20 14:00:46 -05:00
Hexagon [Hexagon] Improve check for HVX types 2020-11-27 13:33:10 -06:00
Inputs
Lanai
MIR OpaquePtr: Bulk update tests to use typed sret 2020-11-20 17:58:26 -05:00
MSP430 OpaquePtr: Bulk update tests to use typed sret 2020-11-20 17:58:26 -05:00
Mips [FastISel] Flush local value map on ever instruction 2020-11-25 13:05:00 -05:00
NVPTX OpaquePtr: Bulk update tests to use typed byval 2020-11-20 14:00:46 -05:00
PowerPC [DAGCombine] Adding a hook to improve the precision of fsqrt if the input is denormal 2020-11-27 02:10:55 +00:00
RISCV [RISCV] Add tests for existing (rotr (bswap X), (i32 16))->grevi pattern for RV32. Extend same pattern to rotl and GREVIW. 2020-11-27 18:09:01 -08:00
SPARC OpaquePtr: Bulk update tests to use typed sret 2020-11-20 17:58:26 -05:00
SystemZ OpaquePtr: Bulk update tests to use typed sret 2020-11-20 17:58:26 -05:00
Thumb OpaquePtr: Update more tests to use typed sret 2020-11-20 20:08:43 -05:00
Thumb2 [ARM] Constant predicate tests. NFC 2020-11-30 09:18:25 +00:00
VE [VE] Optimize prologue/epilogue instructions 2020-11-30 22:22:33 +09:00
WebAssembly OpaquePtr: Bulk update tests to use typed sret 2020-11-20 17:58:26 -05:00
WinCFGuard [CFGuard] Add address-taken IAT tables and delay-load support 2020-11-17 18:24:45 -08:00
WinEH
X86 [X86][AVX512] Only lower to VPALIGNR if we have BWI (PR48322) 2020-11-30 10:51:24 +00:00
XCore OpaquePtr: Bulk update tests to use typed byval 2020-11-20 14:00:46 -05:00