llvm-project/llvm/lib/CodeGen
Fraser Cormack 85e31eddf2 [DAGCombiner] Relax an assertion to an early return
The select-of-constants transform was asserting that its constant vector
inputs did not implicitly truncate their input without that as an
explicit precondition to the function. This patch relaxes that assertion
into an early return to skip the optimization.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D102393
2021-05-17 09:15:55 +01:00
..
AsmPrinter Support GCC's -fstack-usage flag 2021-05-15 10:22:49 -07:00
GlobalISel [GlobalISel][CallLowering] Fix crash when handling a v3s32 type that's being passed as v2s64. 2021-05-14 16:30:51 -07:00
LiveDebugValues [ADT] Make TrackingStatistic's ctor constexpr 2021-04-28 12:00:17 +02:00
MIRParser [SystemZ][z/OS] Add IsText Argument to GetFile and GetFileOrSTDIN 2021-04-16 10:08:36 -04:00
SelectionDAG [DAGCombiner] Relax an assertion to an early return 2021-05-17 09:15:55 +01:00
AggressiveAntiDepBreaker.cpp [CodeGen] Use range-based for loops (NFC) 2021-02-15 14:46:11 -08:00
AggressiveAntiDepBreaker.h
AllocationOrder.cpp [NFC][regalloc] Unit test for AllocationOrder iteration. 2020-09-29 10:48:07 -07:00
AllocationOrder.h [NFC] Use [MC]Register in RegAllocGreedy 2020-10-23 11:30:53 -07:00
Analysis.cpp [Analysis] Attribute alignment should not prevent tail call optimization 2021-04-24 19:57:42 +02:00
AtomicExpandPass.cpp Copy syncscope when expanding atomicrmw into cmpxchg loop 2021-04-05 17:29:38 -07:00
BasicBlockSections.cpp Change void getNoop(MCInst &NopInst) to MCInst getNop() 2021-03-15 12:05:34 -07:00
BasicTargetTransformInfo.cpp
BranchFolding.cpp [CSSPGO] Flip SkipPseudoOp to true for MIR APIs. 2021-04-19 17:55:34 -07:00
BranchFolding.h Fix some clang-tidy bugprone-argument-comment issues 2020-09-19 20:41:25 -07:00
BranchRelaxation.cpp [AArch64] Enable implicit null check transformation 2020-09-17 16:00:19 -07:00
BreakFalseDeps.cpp [NFC][MC] Use MCRegister for ReachingDefAnalysis APIs 2020-10-22 08:47:35 -07:00
CFGuardLongjmp.cpp Revert rG5dd566b7c7b78bd- "PassManager.h - remove unnecessary Function.h/Module.h includes. NFCI." 2020-07-24 13:02:33 +01:00
CFIInstrInserter.cpp Introduce a generic operator to apply complex operations to BitVector 2021-03-23 14:23:26 +01:00
CMakeLists.txt [GC][NFC] Move GCStrategy from CodeGen to IR 2021-05-13 12:31:59 +07:00
CalcSpillWeights.cpp [RegAlloc] Fix "ran out of regs" with uses in statepoint 2021-03-24 10:25:34 +07:00
CallingConvLower.cpp [SVE] Deal with SVE tuple call arguments correctly when running out of registers 2020-11-12 08:41:50 +00:00
CodeGen.cpp [NFC][CodeGen] Split DwarfEHPrepare pass into an actual transform and an legacy-PM wrapper 2021-01-02 01:01:19 +03:00
CodeGenPassBuilder.cpp Reland "[NewPM][CodeGen] Introduce CodeGenPassBuilder to help build codegen pipeline" (again) 2020-12-29 16:39:55 -08:00
CodeGenPrepare.cpp [CPG][ARM] Optimize towards branch on zero in codegenprepare 2021-05-16 17:54:06 +01:00
CommandFlags.cpp [Debug-Info] add -gstrict-dwarf support in backend 2021-05-12 23:00:52 -04:00
CriticalAntiDepBreaker.cpp [CodeGen] Use range-based for loops (NFC) 2021-02-12 23:44:33 -08:00
CriticalAntiDepBreaker.h
DFAPacketizer.cpp [NFC][AA] Prepare to convert AliasResult to class with PartialAlias offset. 2021-04-09 12:54:22 +03:00
DeadMachineInstructionElim.cpp [CodeGen] Use range-based for loops (NFC) 2021-02-12 23:44:33 -08:00
DetectDeadLanes.cpp DetectDeadLanes.cpp - remove unused headers. NFCI. 2020-11-25 11:38:28 +00:00
DwarfEHPrepare.cpp [CodeGen][DwarfEHPrepare] Preserve Dominator Tree 2021-01-28 14:11:34 +03:00
EHContGuardCatchret.cpp Add ehcont section support 2021-02-15 14:27:12 +08:00
EarlyIfConversion.cpp [EarlyIfConversion] Avoid producing selects with identical operands 2021-04-30 15:51:14 -07:00
EdgeBundles.cpp [docs] Fix doxygen comments wrongly attached to the llvm namespace 2021-04-07 01:20:18 +02:00
ExecutionDomainFix.cpp ExecutionDomainFix.cpp - use const refs in for-range loops. NFCI. 2021-01-27 15:39:32 +00:00
ExpandMemCmp.cpp [ExpandMemCmpPass] Preserve Dominator Tree, if available 2021-01-30 01:14:51 +03:00
ExpandPostRAPseudos.cpp [CodeGen] Use range-based for loops (NFC) 2021-02-12 23:44:33 -08:00
ExpandReductions.cpp [ExpandReductions] fix FMF requirement for fmin/fmax 2021-02-04 13:32:08 -05:00
ExpandVectorPredication.cpp Recommit "[VP,Integer,#2] ExpandVectorPredication pass" 2021-05-04 11:47:52 +02:00
FEntryInserter.cpp
FaultMaps.cpp [FaultsMaps][llvm-objdump] Move FaultMapParser to Object/. Remove CodeGen dependency from llvm-objdump 2021-01-27 10:39:59 -08:00
FinalizeISel.cpp
FixupStatepointCallerSaved.cpp [Statepoint] Handle 'undef' operand tied to def 2021-02-03 10:41:14 +07:00
FuncletLayout.cpp
GCMetadata.cpp [GC][NFC] Move GCStrategy from CodeGen to IR 2021-05-13 12:31:59 +07:00
GCMetadataPrinter.cpp
GCRootLowering.cpp [GC][NFC] Move GCStrategy from CodeGen to IR 2021-05-13 12:31:59 +07:00
GlobalMerge.cpp [SVE][CodeGen] Replace use of TypeSize operator< in GlobalMerge::doMerge 2020-10-01 14:06:59 +01:00
HardwareLoops.cpp [ARM] Improve WLS lowering 2021-03-11 17:56:19 +00:00
IfConversion.cpp IfConverter::MeetIfcvtSizeLimit - Fix uninitialized variable warnings. NFCI. 2021-05-15 14:51:54 +01:00
ImplicitNullChecks.cpp [NFC][AA] Prepare to convert AliasResult to class with PartialAlias offset. 2021-04-09 12:54:22 +03:00
IndirectBrExpandPass.cpp [CodeGen] IndirectBrExpandPass: preserve Dominator Tree, if available 2021-01-28 01:58:53 +03:00
InlineSpiller.cpp [GreedyRA] Add support for invoke statepoint with tied-defs. 2021-05-05 11:13:35 +07:00
InterferenceCache.cpp [NFC][regalloc] Use MCRegister instead of unsigned in InterferenceCache 2020-10-07 14:48:43 -07:00
InterferenceCache.h [NFC][regalloc] Use MCRegister instead of unsigned in InterferenceCache 2020-10-07 14:48:43 -07:00
InterleavedAccessPass.cpp [llvm] Use append_range (NFC) 2021-01-27 23:25:41 -08:00
InterleavedLoadCombinePass.cpp [CodeGen, DebugInfo] Use llvm::find_if (NFC) 2021-01-10 09:24:53 -08:00
IntrinsicLowering.cpp Introduce llvm.noalias.decl intrinsic 2021-01-16 09:20:45 +01:00
LLVMTargetMachine.cpp Add -fbinutils-version= to gate ELF features on the specified binutils version 2021-01-26 12:28:23 -08:00
LatencyPriorityQueue.cpp [CodeGen] Use range-based for loops (NFC) 2021-02-13 20:41:39 -08:00
LazyMachineBlockFrequencyInfo.cpp
LexicalScopes.cpp [CSSPGO] Exclude pseudo probes from slot index 2021-04-19 17:55:35 -07:00
LiveDebugVariables.cpp Reapply "[DebugInfo] Drop DBG_VALUE_LISTs with an excessive number of debug operands" 2021-05-07 14:55:02 +01:00
LiveDebugVariables.h [LiveDebugVariables] Delete unneeded doInitialization 2020-09-04 13:27:42 -07:00
LiveInterval.cpp [CodeGen] Use range-based for loops (NFC) 2021-02-21 19:58:07 -08:00
LiveIntervalCalc.cpp [llvm] Ensure newlines at the end of files (NFC) 2021-01-10 09:24:57 -08:00
LiveIntervalUnion.cpp [regalloc] Ensure Query::collectInterferringVregs is called before interval iteration 2021-04-01 08:33:28 -07:00
LiveIntervals.cpp [CSSPGO] Exclude pseudo probes from slot index 2021-04-19 17:55:35 -07:00
LivePhysRegs.cpp [CodeGen] Use range-based for loops (NFC) 2021-02-13 20:41:39 -08:00
LiveRangeCalc.cpp [llvm] Use llvm::lower_bound and llvm::upper_bound (NFC) 2021-01-29 23:23:36 -08:00
LiveRangeEdit.cpp [NFC][Regalloc] Share the VirtRegAuxInfo object with LiveRangeEdit 2021-02-19 07:44:28 -08:00
LiveRangeShrink.cpp [CSSPGO] Exclude pseudo probes from slot index 2021-04-19 17:55:35 -07:00
LiveRangeUtils.h [docs] Fix doxygen comments wrongly attached to the llvm namespace 2021-04-07 01:20:18 +02:00
LiveRegMatrix.cpp [regalloc] Ensure Query::collectInterferringVregs is called before interval iteration 2021-04-01 08:33:28 -07:00
LiveRegUnits.cpp [ARM][RegisterScavenging] Don't consider LR liveout if it is not reloaded 2021-01-28 09:22:55 +00:00
LiveStacks.cpp
LiveVariables.cpp [CSSPGO] Exclude pseudo probes from slot index 2021-04-19 17:55:35 -07:00
LocalStackSlotAllocation.cpp [CodeGen] Use range-based for loops (NFC) 2021-02-13 20:41:39 -08:00
LoopTraversal.cpp
LowLevelType.cpp [GISel] Add new combines for unary FP instrs with constant operand 2020-09-16 10:34:15 -07:00
LowerEmuTLS.cpp [LowerEmuTls] Copy dso_local from <var> to __emutls_v.<var> 2020-12-30 16:11:32 -08:00
MBFIWrapper.cpp [MBFIWrapper] Add a new function getBlockProfileCount 2020-09-23 09:31:45 -07:00
MIRCanonicalizerPass.cpp [CodeGen] Use llvm::append_range (NFC) 2021-01-21 19:59:46 -08:00
MIRNamerPass.cpp
MIRPrinter.cpp MIR: Fix missing serialization for HasTailCall 2021-03-21 13:14:04 -04:00
MIRPrintingPass.cpp
MIRVRegNamerUtils.cpp [MIRVRegNamer] Experimental MachineInstr stable hashing (Fowler-Noll-Vo) 2020-09-03 16:13:09 -04:00
MIRVRegNamerUtils.h
MIRYamlMapping.cpp [AMDGPU] Serialize MFInfo::ScavengeFI 2021-05-07 11:15:25 +02:00
MachineBasicBlock.cpp [CSSPGO] Exclude pseudo probes from slot index 2021-04-19 17:55:35 -07:00
MachineBlockFrequencyInfo.cpp CodeGen: Fix null dereference before null check 2021-05-11 09:07:32 -04:00
MachineBlockPlacement.cpp Internalize some cl::opt global variables or move them under namespace llvm 2021-05-07 11:15:43 -07:00
MachineBranchProbabilityInfo.cpp Internalize some cl::opt global variables or move them under namespace llvm 2021-05-07 11:15:43 -07:00
MachineCSE.cpp [MachineCSE][NFC]: Refactor and comment on preventing CSE for isConvergent instrs 2021-05-05 14:22:03 -07:00
MachineCheckDebugify.cpp [Debugify] Support checking Machine IR debug info 2020-12-16 22:17:25 -08:00
MachineCombiner.cpp [PowerPC] support register pressure reduction in machine combiner. 2021-01-24 21:28:21 -05:00
MachineCopyPropagation.cpp Reapply "[DebugInfo] Fix updateDbgUsersToReg to support DBG_VALUE_LIST" 2021-05-12 10:19:57 +01:00
MachineDebugify.cpp [Debugify] Support checking Machine IR debug info 2020-12-16 22:17:25 -08:00
MachineDominanceFrontier.cpp
MachineDominators.cpp
MachineFrameInfo.cpp [NFC][CodeGen] Tidy up TargetRegisterInfo stack realignment functions 2021-03-30 17:31:39 +01:00
MachineFunction.cpp [llvm][IR] Do not place constants with static relocations in a mergeable section 2021-02-18 15:39:00 -08:00
MachineFunctionPass.cpp [NFC] Reduce include files dependency. 2020-12-03 18:25:05 +03:00
MachineFunctionPrinterPass.cpp [NewPM] Support --print-before/after in NPM 2020-12-03 16:52:14 -08:00
MachineFunctionSplitter.cpp [NFC] Use hasSection instead of getSection().empty() 2021-04-23 10:00:38 -07:00
MachineInstr.cpp [NFC][AA] Prepare to convert AliasResult to class with PartialAlias offset. 2021-04-09 12:54:22 +03:00
MachineInstrBundle.cpp [CodeGen] Use range-based for loops (NFC) 2021-02-15 14:46:11 -08:00
MachineLICM.cpp [MachineLICM] Fix wrong and confusing comment. NFC. 2021-01-29 13:39:07 +00:00
MachineLoopInfo.cpp [MachineLoop] New helper isLoopInvariant() 2021-01-08 09:04:56 +00:00
MachineLoopUtils.cpp [CodeGen] Remove unused function isRegLiveInExitBlocks (NFC) 2021-01-12 21:43:48 -08:00
MachineModuleInfo.cpp [MC] Untangle MCContext and MCObjectFileInfo 2021-05-05 10:03:02 -07:00
MachineModuleInfoImpls.cpp
MachineOperand.cpp [llvm][NFC] Remove remaining deprecated alignment functions from CodeGen 2021-05-07 10:22:41 +00:00
MachineOptimizationRemarkEmitter.cpp
MachineOutliner.cpp Add the use of register r for outlined function when register r is live in and defined later. 2021-03-03 15:14:11 -08:00
MachinePassManager.cpp [NewPM] Hide pass manager debug logging behind -debug-pass-manager-verbose 2021-05-07 21:51:47 -07:00
MachinePipeliner.cpp [NFC][AA] Prepare to convert AliasResult to class with PartialAlias offset. 2021-04-09 12:54:22 +03:00
MachinePostDominators.cpp
MachineRegionInfo.cpp
MachineRegisterInfo.cpp Reapply "[DebugInfo] Add new instruction and DIExpression operator for variadic debug values" 2021-03-05 12:32:05 +00:00
MachineSSAUpdater.cpp [docs] Fix doxygen comments wrongly attached to the llvm namespace 2021-04-07 01:20:18 +02:00
MachineScheduler.cpp [CSSPGO] Exclude pseudo probes from slot index 2021-04-19 17:55:35 -07:00
MachineSink.cpp [CSSPGO] Exclude pseudo probes from slot index 2021-04-19 17:55:35 -07:00
MachineSizeOpts.cpp Revert rG5dd566b7c7b78bd- "PassManager.h - remove unnecessary Function.h/Module.h includes. NFCI." 2020-07-24 13:02:33 +01:00
MachineStableHash.cpp MachineStableHash.h - remove MachineInstr.h include. NFC. 2020-09-07 13:33:48 +01:00
MachineStripDebug.cpp
MachineTraceMetrics.cpp [NFC][MC] Type [MC]Register uses in MachineTraceMetrics 2020-10-19 09:49:52 -07:00
MachineVerifier.cpp GlobalISel: Relax verification of physical register copy types 2021-04-28 08:45:41 -04:00
MacroFusion.cpp Revert "[NFC][ScheduleDAG] Remove unused EntrySU SUnit" 2020-09-21 13:33:05 +02:00
ModuloSchedule.cpp ModuloSchedule.cpp - remove unnecessary includes. NFCI. 2020-09-17 16:47:48 +01:00
MultiHazardRecognizer.cpp [CodeGen, Transforms] Use llvm::any_of (NFC) 2020-12-24 09:08:36 -08:00
NonRelocatableStringpool.cpp
OptimizePHIs.cpp [CodeGen] Use range-based for loops (NFC) 2021-02-17 23:58:46 -08:00
PHIElimination.cpp Make sure PHIElimination doesn't copy debug locations across basic blocks. 2021-04-20 17:03:29 -07:00
PHIEliminationUtils.cpp PR47468: Fix findPHICopyInsertPoint, so that copies aren't incorrectly inserted after an INLINEASM_BR. 2020-09-18 14:14:04 -04:00
PHIEliminationUtils.h
ParallelCG.cpp [LTO] Update splitCodeGen to take a reference to the module. (NFC) 2021-01-29 11:53:11 +00:00
PatchableFunction.cpp
PeepholeOptimizer.cpp Make LLVM build in C++20 mode 2020-12-17 10:44:10 +00:00
PostRAHazardRecognizer.cpp [HazardRec] Allow inserting multiple wait-states simultaneously 2020-10-20 17:03:47 -07:00
PostRASchedulerList.cpp Revert "[NFC][ScheduleDAG] Remove unused EntrySU SUnit" 2020-09-21 13:33:05 +02:00
PreISelIntrinsicLowering.cpp [CodeGen] Construct SmallVector with iterator ranges (NFC) 2020-12-31 09:39:11 -08:00
ProcessImplicitDefs.cpp [CodeGen] Use range-based for loops (NFC) 2021-02-17 23:58:46 -08:00
PrologEpilogInserter.cpp IR+AArch64: add a "swiftasync" argument attribute. 2021-05-14 11:43:58 +01:00
PseudoProbeInserter.cpp [CSSPGO] Deduplicating dangling pseudo probes. 2021-03-03 22:44:42 -08:00
PseudoSourceValue.cpp
RDFGraph.cpp [CodeGen] Use range-based for loops (NFC) 2021-02-17 23:58:46 -08:00
RDFLiveness.cpp Fix a range-loop-analysis warning. 2021-02-23 14:41:08 -08:00
RDFRegisters.cpp [NFC][MC] Use MCRegister for ReachingDefAnalysis APIs 2020-10-22 08:47:35 -07:00
README.txt
ReachingDefAnalysis.cpp [llvm] Use set_is_subset (NFC) 2021-02-28 10:59:20 -08:00
RegAllocBase.cpp RegAlloc: Fix assert if all registers in class reserved 2021-01-31 11:10:04 -05:00
RegAllocBase.h [NFC][MC] Use MCRegister in LiveRangeMatrix 2020-10-12 08:54:36 -07:00
RegAllocBasic.cpp [NFC][Regalloc] Share the VirtRegAuxInfo object with LiveRangeEdit 2021-02-19 07:44:28 -08:00
RegAllocFast.cpp [RegAllocFast] properly handle STATEPOINT instruction. 2021-05-11 17:27:00 +07:00
RegAllocGreedy.cpp [CSSPGO] Fix an AV caused by a block that has only pseudo pseudo instructions. 2021-04-27 17:54:34 -07:00
RegAllocPBQP.cpp [SystemZ][z/OS][Windows] Add new OF_TextWithCRLF flag and use this flag instead of OF_Text 2021-04-06 07:23:31 -04:00
RegUsageInfoCollector.cpp
RegUsageInfoPropagate.cpp
RegisterClassInfo.cpp Support a list of CostPerUse values 2021-01-29 10:14:52 +05:30
RegisterCoalescer.cpp [CSSPGO] Exclude pseudo probes from slot index 2021-04-19 17:55:35 -07:00
RegisterCoalescer.h [NFC] Use [MC]Register in RegAllocPBQP & RegisterCoalescer 2020-10-26 17:13:32 -07:00
RegisterPressure.cpp [CSSPGO] Exclude pseudo probes from slot index 2021-04-19 17:55:35 -07:00
RegisterScavenging.cpp [CSSPGO] Exclude pseudo probes from slot index 2021-04-19 17:55:35 -07:00
RegisterUsageInfo.cpp
RenameIndependentSubregs.cpp [NFC][Regalloc] accessors for 'reg' and 'weight' 2020-09-16 08:28:57 -07:00
ReplaceWithVeclib.cpp [CodeGen] New pass: Replace vector intrinsics with call to vector library 2021-02-12 12:53:27 -05:00
ResetMachineFunctionPass.cpp
SafeStack.cpp [CodeGen] SafeStack: preserve DominatorTree if it is avaliable 2021-01-27 18:32:35 +03:00
SafeStackLayout.cpp [llvm] Use the default value of drop_begin (NFC) 2021-01-18 10:16:36 -08:00
SafeStackLayout.h
ScheduleDAG.cpp Revert "[NFC][ScheduleDAG] Remove unused EntrySU SUnit" 2020-09-21 13:33:05 +02:00
ScheduleDAGInstrs.cpp [CSSPGO] Exclude pseudo probes from slot index 2021-04-19 17:55:35 -07:00
ScheduleDAGPrinter.cpp [DDG] Data Dependence Graph - DOT printer - recommit 2020-12-16 12:37:36 -05:00
ScoreboardHazardRecognizer.cpp
ShadowStackGCLowering.cpp Revert "Allow invokable sub-classes of IntrinsicInst" 2021-04-20 15:38:38 -07:00
ShrinkWrap.cpp [ShrinkWrap] Delete unneeded nullptr checks for the save point. NFC 2020-10-22 00:27:01 -07:00
SjLjEHPrepare.cpp [CodeGen] Construct SmallVector with iterator ranges (NFC) 2020-12-31 09:39:11 -08:00
SlotIndexes.cpp [CSSPGO] Exclude pseudo probes from slot index 2021-04-19 17:55:35 -07:00
SpillPlacement.cpp [CodeGen] Use range-based for loops (NFC) 2021-02-18 22:46:43 -08:00
SpillPlacement.h [regalloc] Add a couple of dump routines for ease of debugging [NFC] 2021-02-18 08:50:00 -08:00
SplitKit.cpp [GreedyRA] Add support for invoke statepoint with tied-defs. 2021-05-05 11:13:35 +07:00
SplitKit.h [GreedyRA] Add support for invoke statepoint with tied-defs. 2021-05-05 11:13:35 +07:00
StackColoring.cpp [CodeGen] Use range-based for loops (NFC) 2021-02-19 22:44:14 -08:00
StackMapLivenessAnalysis.cpp
StackMaps.cpp [NFC][CodeGen] Tidy up TargetRegisterInfo stack realignment functions 2021-03-30 17:31:39 +01:00
StackProtector.cpp Revert "Allow invokable sub-classes of IntrinsicInst" 2021-04-20 15:38:38 -07:00
StackSlotColoring.cpp [CodeGen] Use range-based for loops (NFC) 2021-02-18 22:46:43 -08:00
SwiftErrorValueTracking.cpp [CodeGen, DebugInfo] Use llvm::find_if (NFC) 2021-01-10 09:24:53 -08:00
SwitchLoweringUtils.cpp SwitchLoweringUtils.h - reduce TargetLowering.h include. NFCI. 2020-09-10 17:42:18 +01:00
TailDuplication.cpp
TailDuplicator.cpp [CSSPGO] Unblocking optimizations by dangling pseudo probes. 2021-03-03 22:44:42 -08:00
TargetFrameLoweringImpl.cpp [SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference. 2020-11-05 11:02:18 +00:00
TargetInstrInfo.cpp [Statepoint] Factor-out utility function to get non-foldable area of STATEPOINT like instructions. NFC 2021-04-06 11:44:37 +07:00
TargetLoweringBase.cpp [TargetLowering] Improve legalization of scalable vector types 2021-05-12 16:33:07 +01:00
TargetLoweringObjectFileImpl.cpp [WebAssembly] Add TLS data segment flag: WASM_SEG_FLAG_TLS 2021-05-12 13:31:02 -07:00
TargetOptionsImpl.cpp [DWARF] Avoid entry_values production for SCE 2020-07-24 13:34:05 +02:00
TargetPassConfig.cpp [X86] Support AMX fast register allocation 2021-05-08 14:21:11 +08:00
TargetRegisterInfo.cpp [TargetRegisterInfo] Speed up getAllocatableSet. NFCI. 2021-05-12 14:09:05 +01:00
TargetSchedule.cpp
TargetSubtargetInfo.cpp [X86][MC][Target] Initial backend support a tune CPU to support -mtune 2020-08-14 15:31:50 -07:00
TwoAddressInstructionPass.cpp [NFC] Replace loop by idiomatic llvm::find_if 2021-03-16 12:49:19 +01:00
TypePromotion.cpp [TTI] Return a TypeSize from getRegisterBitWidth. 2021-03-24 14:45:13 +00:00
UnreachableBlockElim.cpp [CodeGen] Use range-based for loops (NFC) 2021-02-20 21:46:02 -08:00
ValueTypes.cpp [ValueTypes] Add MVTs for v256i16 and v256f16 2021-05-04 18:06:13 +01:00
VirtRegMap.cpp VirtRegMap: Support partially allocated virtual registers 2021-04-29 21:51:05 -04:00
WasmEHPrepare.cpp [WebAssembly] Disable uses of __clang_call_terminate 2021-03-04 14:26:35 -08:00
WinEHPrepare.cpp [CodeGen] Use range-based for loops (NFC) 2021-02-21 19:58:07 -08:00
XRayInstrumentation.cpp [xray] Honor xray-never function-instrument attribute 2021-01-19 18:47:09 -05:00

README.txt

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str r4, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %noreg, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side
effects).  Once this is in place, it would be even better to have tblgen
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStacks analysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.