forked from OSchip/llvm-project
503 lines
12 KiB
YAML
503 lines
12 KiB
YAML
# RUN: llc -mtriple arm-- -global-isel -run-pass=legalizer %s -o - | FileCheck %s
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--- |
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define void @test_sext_s8() { ret void }
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define void @test_zext_s16() { ret void }
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define void @test_add_s8() { ret void }
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define void @test_add_s16() { ret void }
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define void @test_add_s32() { ret void }
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define void @test_sub_s8() { ret void }
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define void @test_sub_s16() { ret void }
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define void @test_sub_s32() { ret void }
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define void @test_mul_s8() { ret void }
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define void @test_mul_s16() { ret void }
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define void @test_mul_s32() { ret void }
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define void @test_load_from_stack() { ret void }
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define void @test_legal_loads() #0 { ret void }
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define void @test_legal_stores() #0 { ret void }
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define void @test_gep() { ret void }
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define void @test_constants() { ret void }
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define void @test_fadd_s32() #0 { ret void }
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define void @test_fadd_s64() #0 { ret void }
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attributes #0 = { "target-features"="+vfp2" }
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...
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---
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name: test_sext_s8
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# CHECK-LABEL: name: test_sext_s8
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.0:
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liveins: %r0
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%0(s8) = COPY %r0
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%1(s32) = G_SEXT %0
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; G_SEXT with s8 is legal, so we should find it unchanged in the output
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; CHECK: {{%[0-9]+}}(s32) = G_SEXT {{%[0-9]+}}
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%r0 = COPY %1(s32)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_zext_s16
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# CHECK-LABEL: name: test_zext_s16
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.0:
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liveins: %r0
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%0(s16) = COPY %r0
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%1(s32) = G_ZEXT %0
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; G_ZEXT with s16 is legal, so we should find it unchanged in the output
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; CHECK: {{%[0-9]+}}(s32) = G_ZEXT {{%[0-9]+}}
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%r0 = COPY %1(s32)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_add_s8
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# CHECK-LABEL: name: test_add_s8
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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%0(s8) = COPY %r0
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%1(s8) = COPY %r1
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%2(s8) = G_ADD %0, %1
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; G_ADD with s8 should widen
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; CHECK: {{%[0-9]+}}(s32) = G_ADD {{%[0-9]+, %[0-9]+}}
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; CHECK-NOT: {{%[0-9]+}}(s8) = G_ADD {{%[0-9]+, %[0-9]+}}
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%r0 = COPY %2(s8)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_add_s16
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# CHECK-LABEL: name: test_add_s16
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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%0(s16) = COPY %r0
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%1(s16) = COPY %r1
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%2(s16) = G_ADD %0, %1
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; G_ADD with s16 should widen
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; CHECK: {{%[0-9]+}}(s32) = G_ADD {{%[0-9]+, %[0-9]+}}
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; CHECK-NOT: {{%[0-9]+}}(s16) = G_ADD {{%[0-9]+, %[0-9]+}}
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%r0 = COPY %2(s16)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_add_s32
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# CHECK-LABEL: name: test_add_s32
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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%0(s32) = COPY %r0
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%1(s32) = COPY %r1
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%2(s32) = G_ADD %0, %1
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; G_ADD with s32 is legal, so we should find it unchanged in the output
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; CHECK: {{%[0-9]+}}(s32) = G_ADD {{%[0-9]+, %[0-9]+}}
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%r0 = COPY %2(s32)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_sub_s8
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# CHECK-LABEL: name: test_sub_s8
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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%0(s8) = COPY %r0
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%1(s8) = COPY %r1
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%2(s8) = G_SUB %0, %1
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; G_SUB with s8 should widen
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; CHECK: {{%[0-9]+}}(s32) = G_SUB {{%[0-9]+, %[0-9]+}}
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; CHECK-NOT: {{%[0-9]+}}(s8) = G_SUB {{%[0-9]+, %[0-9]+}}
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%r0 = COPY %2(s8)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_sub_s16
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# CHECK-LABEL: name: test_sub_s16
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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%0(s16) = COPY %r0
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%1(s16) = COPY %r1
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%2(s16) = G_SUB %0, %1
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; G_SUB with s16 should widen
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; CHECK: {{%[0-9]+}}(s32) = G_SUB {{%[0-9]+, %[0-9]+}}
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; CHECK-NOT: {{%[0-9]+}}(s16) = G_SUB {{%[0-9]+, %[0-9]+}}
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%r0 = COPY %2(s16)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_sub_s32
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# CHECK-LABEL: name: test_sub_s32
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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%0(s32) = COPY %r0
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%1(s32) = COPY %r1
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%2(s32) = G_SUB %0, %1
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; G_SUB with s32 is legal, so we should find it unchanged in the output
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; CHECK: {{%[0-9]+}}(s32) = G_SUB {{%[0-9]+, %[0-9]+}}
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%r0 = COPY %2(s32)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_mul_s8
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# CHECK-LABEL: name: test_mul_s8
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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%0(s8) = COPY %r0
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%1(s8) = COPY %r1
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%2(s8) = G_MUL %0, %1
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; G_MUL with s8 should widen
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; CHECK: {{%[0-9]+}}(s32) = G_MUL {{%[0-9]+, %[0-9]+}}
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; CHECK-NOT: {{%[0-9]+}}(s8) = G_MUL {{%[0-9]+, %[0-9]+}}
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%r0 = COPY %2(s8)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_mul_s16
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# CHECK-LABEL: name: test_mul_s16
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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%0(s16) = COPY %r0
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%1(s16) = COPY %r1
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%2(s16) = G_MUL %0, %1
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; G_MUL with s16 should widen
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; CHECK: {{%[0-9]+}}(s32) = G_MUL {{%[0-9]+, %[0-9]+}}
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; CHECK-NOT: {{%[0-9]+}}(s16) = G_MUL {{%[0-9]+, %[0-9]+}}
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%r0 = COPY %2(s16)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_mul_s32
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# CHECK-LABEL: name: test_mul_s32
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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%0(s32) = COPY %r0
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%1(s32) = COPY %r1
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%2(s32) = G_MUL %0, %1
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; G_MUL with s32 is legal, so we should find it unchanged in the output
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; CHECK: {{%[0-9]+}}(s32) = G_MUL {{%[0-9]+, %[0-9]+}}
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%r0 = COPY %2(s32)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_load_from_stack
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# CHECK-LABEL: name: test_load_from_stack
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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- { id: 3, class: _ }
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fixedStack:
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- { id: 0, offset: 0, size: 4, alignment: 4, isImmutable: true, isAliased: false }
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- { id: 1, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
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- { id: 2, offset: 8, size: 4, alignment: 4, isImmutable: true, isAliased: false }
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# CHECK: id: [[FRAME_INDEX:[0-9]+]], type: default, offset: 8
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body: |
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bb.0:
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liveins: %r0, %r1, %r2, %r3
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; This is legal, so we should find it unchanged in the output
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; CHECK: [[FIVREG:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[FRAME_INDEX]]
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; CHECK: {{%[0-9]+}}(s32) = G_LOAD [[FIVREG]](p0) :: (load 4)
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%0(p0) = G_FRAME_INDEX %fixed-stack.2
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%1(s32) = G_LOAD %0(p0) :: (load 4)
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BX_RET 14, _
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...
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---
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name: test_legal_loads
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# CHECK-LABEL: name: test_legal_loads
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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- { id: 3, class: _ }
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- { id: 4, class: _ }
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- { id: 5, class: _ }
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- { id: 6, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1, %r2, %r3
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; These are all legal, so we should find them unchanged in the output
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; CHECK-DAG: {{%[0-9]+}}(s64) = G_LOAD %0
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; CHECK-DAG: {{%[0-9]+}}(s32) = G_LOAD %0
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; CHECK-DAG: {{%[0-9]+}}(s16) = G_LOAD %0
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; CHECK-DAG: {{%[0-9]+}}(s8) = G_LOAD %0
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; CHECK-DAG: {{%[0-9]+}}(s1) = G_LOAD %0
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; CHECK-DAG: {{%[0-9]+}}(p0) = G_LOAD %0
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%0(p0) = COPY %r0
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%1(s32) = G_LOAD %0(p0) :: (load 4)
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%2(s16) = G_LOAD %0(p0) :: (load 2)
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%3(s8) = G_LOAD %0(p0) :: (load 1)
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%4(s1) = G_LOAD %0(p0) :: (load 1)
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%5(p0) = G_LOAD %0(p0) :: (load 4)
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%6(s64) = G_LOAD %0(p0) :: (load 8)
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BX_RET 14, _
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...
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---
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name: test_legal_stores
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# CHECK-LABEL: name: test_legal_stores
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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- { id: 3, class: _ }
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- { id: 4, class: _ }
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- { id: 5, class: _ }
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- { id: 6, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1, %r2, %r3, %r4, %r5, %r6, %d1
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; These are all legal, so we should find them unchanged in the output
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; CHECK-DAG: G_STORE {{%[0-9]+}}(s64), %0(p0)
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; CHECK-DAG: G_STORE {{%[0-9]+}}(s32), %0(p0)
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; CHECK-DAG: G_STORE {{%[0-9]+}}(s16), %0(p0)
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; CHECK-DAG: G_STORE {{%[0-9]+}}(s8), %0(p0)
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; CHECK-DAG: G_STORE {{%[0-9]+}}(s1), %0(p0)
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; CHECK-DAG: G_STORE {{%[0-9]+}}(p0), %0(p0)
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%0(p0) = COPY %r0
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%1(s64) = COPY %d1
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G_STORE %1(s64), %0(p0) :: (store 8)
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%2(s32) = COPY %r2
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G_STORE %2(s32), %0(p0) :: (store 4)
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%3(s16) = COPY %r3
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G_STORE %3(s16), %0(p0) :: (store 2)
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%4(s8) = COPY %r4
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G_STORE %4(s8), %0(p0) :: (store 1)
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%5(s1) = COPY %r5
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G_STORE %5(s1), %0(p0) :: (store 1)
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%6(p0) = COPY %r6
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G_STORE %6(p0), %0(p0) :: (store 4)
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BX_RET 14, _
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...
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---
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name: test_gep
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# CHECK-LABEL: name: test_gep
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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%0(p0) = COPY %r0
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%1(s32) = COPY %r1
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; CHECK: {{%[0-9]+}}(p0) = G_GEP {{%[0-9]+}}, {{%[0-9]+}}(s32)
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%2(p0) = G_GEP %0, %1(s32)
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%r0 = COPY %2(p0)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_constants
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# CHECK-LABEL: name: test_constants
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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body: |
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bb.0:
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%0(s32) = G_CONSTANT 42
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; CHECK: {{%[0-9]+}}(s32) = G_CONSTANT 42
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%r0 = COPY %0(s32)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_fadd_s32
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# CHECK-LABEL: name: test_fadd_s32
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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|
- { id: 2, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0, %r1
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s32) = COPY %r1
|
|
%2(s32) = G_FADD %0, %1
|
|
; G_FADD with s32 is legal, so we should find it unchanged in the output
|
|
; CHECK: {{%[0-9]+}}(s32) = G_FADD {{%[0-9]+, %[0-9]+}}
|
|
%r0 = COPY %2(s32)
|
|
BX_RET 14, _, implicit %r0
|
|
|
|
...
|
|
---
|
|
name: test_fadd_s64
|
|
# CHECK-LABEL: name: test_fadd_s64
|
|
legalized: false
|
|
# CHECK: legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %d0, %d1
|
|
|
|
%0(s64) = COPY %d0
|
|
%1(s64) = COPY %d1
|
|
%2(s64) = G_FADD %0, %1
|
|
; G_FADD with s64 is legal, so we should find it unchanged in the output
|
|
; CHECK: {{%[0-9]+}}(s64) = G_FADD {{%[0-9]+, %[0-9]+}}
|
|
%d0 = COPY %2(s64)
|
|
BX_RET 14, _, implicit %d0
|
|
|
|
...
|