forked from OSchip/llvm-project
124 lines
5.0 KiB
C++
124 lines
5.0 KiB
C++
//===- SystemZInstrInfo.h - SystemZ Instruction Information -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the SystemZ implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_SYSTEMZINSTRINFO_H
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#define LLVM_TARGET_SYSTEMZINSTRINFO_H
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#include "SystemZ.h"
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#include "SystemZRegisterInfo.h"
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#include "llvm/ADT/IndexedMap.h"
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#include "llvm/Target/TargetInstrInfo.h"
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namespace llvm {
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class SystemZTargetMachine;
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/// SystemZII - This namespace holds all of the target specific flags that
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/// instruction info tracks.
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///
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namespace SystemZII {
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enum {
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//===------------------------------------------------------------------===//
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// SystemZ Specific MachineOperand flags.
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MO_NO_FLAG = 0,
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/// MO_GOTENT - On a symbol operand this indicates that the immediate is
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/// the offset to the location of the symbol name from the base of the GOT.
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///
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/// SYMBOL_LABEL @GOTENT
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MO_GOTENT = 1,
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/// MO_PLT - On a symbol operand this indicates that the immediate is
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/// offset to the PLT entry of symbol name from the current code location.
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///
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/// SYMBOL_LABEL @PLT
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MO_PLT = 2
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};
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}
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class SystemZInstrInfo : public TargetInstrInfoImpl {
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const SystemZRegisterInfo RI;
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SystemZTargetMachine &TM;
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IndexedMap<unsigned> RegSpillOffsets;
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public:
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explicit SystemZInstrInfo(SystemZTargetMachine &TM);
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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virtual const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const;
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bool isMoveInstr(const MachineInstr& MI,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
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unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
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unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const;
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virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill,
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int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const;
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virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const;
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bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
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virtual bool AnalyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const;
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const;
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virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
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SystemZCC::CondCodes getOppositeCondition(SystemZCC::CondCodes CC) const;
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SystemZCC::CondCodes getCondFromBranchOpc(unsigned Opc) const;
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const TargetInstrDesc& getBrCond(SystemZCC::CondCodes CC) const;
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const TargetInstrDesc& getLongDispOpc(unsigned Opc) const;
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const TargetInstrDesc& getMemoryInstr(unsigned Opc, int64_t Offset = 0) const {
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if (Offset < 0 || Offset >= 4096)
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return getLongDispOpc(Opc);
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else
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return get(Opc);
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}
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};
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}
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#endif
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