forked from OSchip/llvm-project
341 lines
9.2 KiB
LLVM
341 lines
9.2 KiB
LLVM
; RUN: llc -mtriple=thumbv8.main -mcpu=cortex-m33 %s -arm-disable-cgp=false -o - | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-NODSP
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; RUN: llc -mtriple=thumbv7-linux-android %s -arm-disable-cgp=false -o - | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-NODSP
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; RUN: llc -mtriple=thumbv7em %s -arm-disable-cgp=false -arm-enable-scalar-dsp=true -o - | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-DSP
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; RUN: llc -mtriple=thumbv8 %s -arm-disable-cgp=false -arm-enable-scalar-dsp=true -arm-enable-scalar-dsp-imms=true -o - | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-DSP-IMM
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; Transform will fail because the trunc is not a sink.
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; CHECK-COMMON-LABEL: dsp_trunc
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; CHECK-COMMON: add [[ADD:[^ ]+]],
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; CHECK-DSP-NEXT: ldrh r1, [r3]
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; CHECK-DSP-NEXT: ldrh r2, [r2]
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; CHECK-DSP-NEXT: subs r1, r1, [[ADD]]
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; CHECK-DSP-NEXT: add r0, r2
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; CHECK-DSP-NEXT: uxth r3, r1
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; CHECK-DSP-NEXT: uxth r2, r0
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; CHECK-DSP-NEXT: cmp r2, r3
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; With DSP-IMM, we could have:
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; movs r1, #0
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; uxth r0, r0
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; usub16 r1, r1, r0
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; ldrh r0, [r2]
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; ldrh r3, [r3]
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; usub16 r0, r0, r1
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; uadd16 r1, r3, r1
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; cmp r0, r1
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define i16 @dsp_trunc(i32 %arg0, i32 %arg1, i16* %gep0, i16* %gep1) {
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entry:
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%add0 = add i32 %arg0, %arg1
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%conv0 = trunc i32 %add0 to i16
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%sub0 = sub i16 0, %conv0
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%load0 = load i16, i16* %gep0, align 2
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%load1 = load i16, i16* %gep1, align 2
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%sub1 = sub i16 %load0, %sub0
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%add1 = add i16 %load1, %sub0
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%cmp = icmp ult i16 %sub1, %add1
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%res = select i1 %cmp, i16 %add1, i16 %sub1
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ret i16 %res
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}
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; CHECK-COMMON-LABEL: trunc_i16_i8
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; CHECK-COMMON: ldrh
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; CHECK-COMMON: uxtb
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; CHECK-COMMON: cmp
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define i8 @trunc_i16_i8(i16* %ptr, i16 zeroext %arg0, i8 zeroext %arg1) {
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entry:
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%0 = load i16, i16* %ptr
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%1 = add i16 %0, %arg0
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%2 = trunc i16 %1 to i8
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%3 = icmp ugt i8 %2, %arg1
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%4 = select i1 %3, i8 %2, i8 %arg1
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ret i8 %4
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}
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; The pass perform the transform, but a uxtb will still be inserted to handle
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; the zext to the icmp.
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; CHECK-COMMON-LABEL: icmp_i32_zext:
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; CHECK-COMMON: sub
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; CHECK-COMMON: uxtb
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; CHECK-COMMON: cmp
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define i8 @icmp_i32_zext(i8* %ptr) {
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entry:
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%gep = getelementptr inbounds i8, i8* %ptr, i32 0
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%0 = load i8, i8* %gep, align 1
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%1 = sub nuw nsw i8 %0, 1
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%conv44 = zext i8 %0 to i32
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br label %preheader
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preheader:
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br label %body
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body:
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%2 = phi i8 [ %1, %preheader ], [ %3, %if.end ]
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%si.0274 = phi i32 [ %conv44, %preheader ], [ %inc, %if.end ]
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%conv51266 = zext i8 %2 to i32
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%cmp52267 = icmp eq i32 %si.0274, %conv51266
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br i1 %cmp52267, label %if.end, label %exit
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if.end:
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%inc = add i32 %si.0274, 1
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%gep1 = getelementptr inbounds i8, i8* %ptr, i32 %inc
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%3 = load i8, i8* %gep1, align 1
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br label %body
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exit:
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ret i8 %2
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}
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; Won't don't handle sext
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; CHECK-COMMON-LABEL: icmp_sext_zext_store_i8_i16
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; CHECK-COMMON: ldrb
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; CHECK-COMMON: ldrsh
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define i32 @icmp_sext_zext_store_i8_i16() {
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entry:
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%0 = load i8, i8* getelementptr inbounds ([16 x i8], [16 x i8]* @d_uch, i32 0, i32 2), align 1
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%conv = zext i8 %0 to i16
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store i16 %conv, i16* @sh1, align 2
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%conv1 = zext i8 %0 to i32
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%1 = load i16, i16* getelementptr inbounds ([16 x i16], [16 x i16]* @d_sh, i32 0, i32 2), align 2
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%conv2 = sext i16 %1 to i32
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%cmp = icmp eq i32 %conv1, %conv2
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%conv3 = zext i1 %cmp to i32
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ret i32 %conv3
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}
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; CHECK-COMMON-LABEL: or_icmp_ugt:
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; CHECK-COMMON: ldrb
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; CHECK-COMMON: sub.w
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; CHECK-COMMON-NOT: uxt
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; CHECK-COMMON: cmp.w
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; CHECK-COMMON-NOT: uxt
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; CHECK-COMMON: cmp
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define i1 @or_icmp_ugt(i32 %arg, i8* %ptr) {
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entry:
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%0 = load i8, i8* %ptr
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%1 = zext i8 %0 to i32
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%mul = shl nuw nsw i32 %1, 1
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%add0 = add nuw nsw i32 %mul, 6
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%cmp0 = icmp ne i32 %arg, %add0
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%add1 = add i8 %0, -1
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%cmp1 = icmp ugt i8 %add1, 3
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%or = or i1 %cmp0, %cmp1
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ret i1 %or
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}
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; CHECK-COMMON-LABEL: icmp_switch_trunc:
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; CHECK-COMMON-NOT: uxt
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define i16 @icmp_switch_trunc(i16 zeroext %arg) {
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entry:
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%conv = add nuw i16 %arg, 15
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%mul = mul nuw nsw i16 %conv, 3
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%trunc = trunc i16 %arg to i3
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switch i3 %trunc, label %default [
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i3 0, label %sw.bb
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i3 1, label %sw.bb.i
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]
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sw.bb:
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%cmp0 = icmp ult i16 %mul, 127
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%select = select i1 %cmp0, i16 %mul, i16 127
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br label %exit
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sw.bb.i:
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%cmp1 = icmp ugt i16 %mul, 34
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%select.i = select i1 %cmp1, i16 %mul, i16 34
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br label %exit
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default:
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br label %exit
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exit:
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%res = phi i16 [ %select, %sw.bb ], [ %select.i, %sw.bb.i ], [ %mul, %default ]
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ret i16 %res
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}
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; We currently only handle truncs as sinks, so a uxt will still be needed for
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; the icmp ugt instruction.
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; CHECK-COMMON-LABEL: urem_trunc_icmps
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; CHECK-COMMON: cmp
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; CHECK-COMMON: uxt
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; CHECK-COMMON: cmp
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define void @urem_trunc_icmps(i16** %in, i32* %g, i32* %k) {
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entry:
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%ptr = load i16*, i16** %in, align 4
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%ld = load i16, i16* %ptr, align 2
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%cmp.i = icmp eq i16 %ld, 0
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br i1 %cmp.i, label %exit, label %cond.false.i
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cond.false.i:
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%rem = urem i16 5, %ld
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%extract.t = trunc i16 %rem to i8
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br label %body
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body:
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%cond.in.i.off0 = phi i8 [ %extract.t, %cond.false.i ], [ %add, %for.inc ]
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%cmp = icmp ugt i8 %cond.in.i.off0, 7
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%conv5 = zext i1 %cmp to i32
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store i32 %conv5, i32* %g, align 4
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%.pr = load i32, i32* %k, align 4
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%tobool13150 = icmp eq i32 %.pr, 0
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br i1 %tobool13150, label %for.inc, label %exit
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for.inc:
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%add = add nuw i8 %cond.in.i.off0, 1
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br label %body
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exit:
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ret void
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}
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; CHECK-COMMON-LABEL: phi_feeding_switch
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; CHECK-COMMON: ldrb
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; CHECK-COMMON: uxtb
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define void @phi_feeding_switch(i8* %memblock, i8* %store, i16 %arg) {
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entry:
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%pre = load i8, i8* %memblock, align 1
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%conv = trunc i16 %arg to i8
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br label %header
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header:
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%phi.0 = phi i8 [ %pre, %entry ], [ %count, %latch ]
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%phi.1 = phi i8 [ %conv, %entry ], [ %phi.3, %latch ]
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%phi.2 = phi i8 [ 0, %entry], [ %count, %latch ]
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switch i8 %phi.0, label %default [
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i8 43, label %for.inc.i
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i8 45, label %for.inc.i.i
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]
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for.inc.i:
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%xor = xor i8 %phi.1, 1
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br label %latch
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for.inc.i.i:
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%and = and i8 %phi.1, 3
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br label %latch
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default:
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%sub = sub i8 %phi.0, 1
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%cmp2 = icmp ugt i8 %sub, 4
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br i1 %cmp2, label %latch, label %exit
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latch:
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%phi.3 = phi i8 [ %xor, %for.inc.i ], [ %and, %for.inc.i.i ], [ %phi.2, %default ]
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%count = add nuw i8 %phi.2, 1
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store i8 %count, i8* %store, align 1
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br label %header
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exit:
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ret void
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}
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; Check that %exp requires uxth in all cases, and will also be required to
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; promote %1 for the call - unless we can generate a uadd16.
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; CHECK-COMMON-LABEL: zext_load_sink_call:
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; CHECK-COMMON: uxt
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; uadd16
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; cmp
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; CHECK-COMMON: uxt
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define i32 @zext_load_sink_call(i16* %ptr, i16 %exp) {
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entry:
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%0 = load i16, i16* %ptr, align 4
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%1 = add i16 %exp, 3
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%cmp = icmp eq i16 %0, %exp
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br i1 %cmp, label %exit, label %if.then
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if.then:
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%conv0 = zext i16 %0 to i32
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%conv1 = zext i16 %1 to i32
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%call = tail call arm_aapcs_vfpcc i32 @dummy(i32 %conv0, i32 %conv1)
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br label %exit
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exit:
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%exitval = phi i32 [ %call, %if.then ], [ 0, %entry ]
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ret i32 %exitval
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}
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%class.ae = type { i8 }
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%class.x = type { i8 }
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%class.v = type { %class.q }
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%class.q = type { i16 }
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; CHECK-COMMON-LABEL: trunc_i16_i9_switch
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; CHECK-COMMON-NOT: uxt
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define i32 @trunc_i16_i9_switch(%class.ae* %this) {
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entry:
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%call = tail call %class.x* @_ZNK2ae2afEv(%class.ae* %this)
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%call2 = tail call %class.v* @_ZN1x2acEv(%class.x* %call)
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%0 = getelementptr inbounds %class.v, %class.v* %call2, i32 0, i32 0, i32 0
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%1 = load i16, i16* %0, align 2
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%2 = trunc i16 %1 to i9
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%trunc = and i9 %2, -64
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switch i9 %trunc, label %cleanup.fold.split [
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i9 0, label %cleanup
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i9 -256, label %if.then7
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]
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if.then7:
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%3 = and i16 %1, 7
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%tobool = icmp eq i16 %3, 0
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%cond = select i1 %tobool, i32 2, i32 1
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br label %cleanup
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cleanup.fold.split:
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br label %cleanup
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cleanup:
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%retval.0 = phi i32 [ %cond, %if.then7 ], [ 0, %entry ], [ 2, %cleanup.fold.split ]
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ret i32 %retval.0
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}
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; CHECK-COMMON-LABEL: bitcast_i16
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; CHECK-COMMON-NOT: uxt
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define i16 @bitcast_i16(i16 zeroext %arg0, i16 zeroext %arg1) {
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entry:
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%cast = bitcast i16 12345 to i16
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%add = add nuw i16 %arg0, 1
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%cmp = icmp ule i16 %add, %cast
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%res = select i1 %cmp, i16 %arg1, i16 32657
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ret i16 %res
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}
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; CHECK-COMMON-LABEL: bitcast_i8
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; CHECK-COMMON-NOT: uxt
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define i8 @bitcast_i8(i8 zeroext %arg0, i8 zeroext %arg1) {
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entry:
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%cast = bitcast i8 127 to i8
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%mul = shl nuw i8 %arg0, 1
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%cmp = icmp uge i8 %mul, %arg1
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%res = select i1 %cmp, i8 %cast, i8 128
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ret i8 %res
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}
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; CHECK-COMMON-LABEL: bitcast_i16_minus
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; CHECK-COMMON-NOT: uxt
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define i16 @bitcast_i16_minus(i16 zeroext %arg0, i16 zeroext %arg1) {
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entry:
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%cast = bitcast i16 -12345 to i16
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%xor = xor i16 %arg0, 7
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%cmp = icmp eq i16 %xor, %arg1
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%res = select i1 %cmp, i16 %cast, i16 32657
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ret i16 %res
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}
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; CHECK-COMMON-LABEL: bitcast_i8_minus
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; CHECK-COMMON-NOT: uxt
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define i8 @bitcast_i8_minus(i8 zeroext %arg0, i8 zeroext %arg1) {
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entry:
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%cast = bitcast i8 -127 to i8
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%and = and i8 %arg0, 3
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%cmp = icmp ne i8 %and, %arg1
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%res = select i1 %cmp, i8 %cast, i8 128
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ret i8 %res
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}
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declare %class.x* @_ZNK2ae2afEv(%class.ae*) local_unnamed_addr
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declare %class.v* @_ZN1x2acEv(%class.x*) local_unnamed_addr
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declare i32 @dummy(i32, i32)
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@d_uch = hidden local_unnamed_addr global [16 x i8] zeroinitializer, align 1
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@sh1 = hidden local_unnamed_addr global i16 0, align 2
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@d_sh = hidden local_unnamed_addr global [16 x i16] zeroinitializer, align 2
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