forked from OSchip/llvm-project
31 lines
1.2 KiB
YAML
31 lines
1.2 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
|
# RUN: llc -mtriple armv7-gnueabihf -run-pass instruction-select \
|
|
# RUN: -verify-machineinstrs -o - %s | FileCheck %s
|
|
---
|
|
# Test that we constrain register classes of temporary virtual registers
|
|
# defined by nested instructions built from a Dst Pattern
|
|
#
|
|
# G_FPTOSI selects to a (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR), where
|
|
# COPY_TO_REGCLASS doesn't constrain its source register class. It exposes the
|
|
# bug as we create a tmp reg for VTOSIZS' result and don't constrain its
|
|
# register class as COPY_TO_REGCLASS' source (which is fine) nor as VTOSIZS'
|
|
# destination (which is not).
|
|
#
|
|
# https://bugs.llvm.org/show_bug.cgi?id=35965
|
|
name: test_fptosi
|
|
legalized: true
|
|
regBankSelected: true
|
|
body: |
|
|
bb.1:
|
|
; CHECK-LABEL: name: test_fptosi
|
|
; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
|
|
; CHECK: [[VTOSIZS:%[0-9]+]]:spr = VTOSIZS [[COPY]], 14, $noreg
|
|
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY [[VTOSIZS]]
|
|
; CHECK: $r0 = COPY [[COPY1]]
|
|
; CHECK: MOVPCLR 14, $noreg, implicit $r0
|
|
%0:fprb(s32) = COPY $s0
|
|
%1:gprb(s32) = G_FPTOSI %0(s32)
|
|
$r0 = COPY %1(s32)
|
|
MOVPCLR 14, $noreg, implicit $r0
|
|
...
|