forked from OSchip/llvm-project
1145 lines
28 KiB
YAML
1145 lines
28 KiB
YAML
# RUN: llc -O0 -mtriple arm-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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define void @test_mla() #0 { ret void }
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define void @test_mla_commutative() #0 { ret void }
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define void @test_mla_v5() #1 { ret void }
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define void @test_mls() #2 { ret void }
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define void @test_no_mls() { ret void }
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define void @test_shifts_to_revsh() #0 { ret void }
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define void @test_shifts_to_revsh_commutative() #0 { ret void }
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define void @test_shifts_no_revsh_features() #1 { ret void }
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define void @test_shifts_no_revsh_constants() #0 { ret void }
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define void @test_bicrr() { ret void }
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define void @test_bicrr_commutative() { ret void }
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define void @test_bicri() { ret void }
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define void @test_bicri_commutative_xor() { ret void }
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define void @test_bicri_commutative_and() { ret void }
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define void @test_bicri_commutative_both() { ret void }
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define void @test_pkhbt() #0 { ret void }
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define void @test_pkhbt_commutative() #0 { ret void }
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define void @test_pkhbt_imm16_31() #0 { ret void }
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define void @test_pkhbt_unshifted() #0 { ret void }
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define void @test_pkhtb_imm16() #0 { ret void }
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define void @test_pkhtb_imm1_15() #0 { ret void }
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define void @test_movti16_0xffff() #2 { ret void }
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define void @test_vnmuls() #3 { ret void }
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define void @test_vnmuls_reassociate() #3 { ret void }
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define void @test_vnmuld() #3 { ret void }
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define void @test_vfnmas() #4 { ret void }
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define void @test_vfnmad() #4 { ret void }
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define void @test_vfmss() #4 { ret void }
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define void @test_vfmsd() #4 { ret void }
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define void @test_vfnmss() #4 { ret void }
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attributes #0 = { "target-features"="+v6" }
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attributes #1 = { "target-features"="-v6" }
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attributes #2 = { "target-features"="+v6t2" }
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attributes #3 = { "target-features"="+vfp2" }
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attributes #4 = { "target-features"="+vfp4" }
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...
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---
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name: test_mla
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# CHECK-LABEL: name: test_mla
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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- { id: 4, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1, $r2
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%0(s32) = COPY $r0
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%1(s32) = COPY $r1
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%2(s32) = COPY $r2
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; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
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; CHECK: [[VREGZ:%[0-9]+]]:gprnopc = COPY $r2
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%3(s32) = G_MUL %0, %1
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%4(s32) = G_ADD %3, %2
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; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, $noreg, $noreg
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$r0 = COPY %4(s32)
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; CHECK: $r0 = COPY [[VREGR]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_mla_commutative
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# CHECK-LABEL: name: test_mla_commutative
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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- { id: 4, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1, $r2
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%0(s32) = COPY $r0
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%1(s32) = COPY $r1
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%2(s32) = COPY $r2
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; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
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; CHECK: [[VREGZ:%[0-9]+]]:gprnopc = COPY $r2
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%3(s32) = G_MUL %0, %1
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%4(s32) = G_ADD %2, %3
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; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, $noreg, $noreg
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$r0 = COPY %4(s32)
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; CHECK: $r0 = COPY [[VREGR]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_mla_v5
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# CHECK-LABEL: name: test_mla_v5
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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- { id: 4, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1, $r2
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%0(s32) = COPY $r0
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%1(s32) = COPY $r1
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%2(s32) = COPY $r2
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; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
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; CHECK: [[VREGZ:%[0-9]+]]:gprnopc = COPY $r2
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%3(s32) = G_MUL %0, %1
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%4(s32) = G_ADD %3, %2
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; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLAv5 [[VREGX]], [[VREGY]], [[VREGZ]], 14, $noreg, $noreg
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$r0 = COPY %4(s32)
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; CHECK: $r0 = COPY [[VREGR]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_mls
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# CHECK-LABEL: name: test_mls
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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- { id: 4, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1, $r2
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%0(s32) = COPY $r0
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%1(s32) = COPY $r1
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%2(s32) = COPY $r2
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; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
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; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
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; CHECK: [[VREGZ:%[0-9]+]]:gpr = COPY $r2
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%3(s32) = G_MUL %0, %1
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%4(s32) = G_SUB %2, %3
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; CHECK: [[VREGR:%[0-9]+]]:gpr = MLS [[VREGX]], [[VREGY]], [[VREGZ]], 14, $noreg
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$r0 = COPY %4(s32)
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; CHECK: $r0 = COPY [[VREGR]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_no_mls
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# CHECK-LABEL: name: test_no_mls
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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- { id: 4, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1, $r2
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%0(s32) = COPY $r0
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%1(s32) = COPY $r1
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%2(s32) = COPY $r2
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; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
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; CHECK: [[VREGZ:%[0-9]+]]:gpr = COPY $r2
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%3(s32) = G_MUL %0, %1
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%4(s32) = G_SUB %2, %3
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; CHECK: [[VREGM:%[0-9]+]]:gprnopc = MULv5 [[VREGX]], [[VREGY]], 14, $noreg, $noreg
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; CHECK: [[VREGR:%[0-9]+]]:gpr = SUBrr [[VREGZ]], [[VREGM]], 14, $noreg, $noreg
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$r0 = COPY %4(s32)
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; CHECK: $r0 = COPY [[VREGR]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_shifts_to_revsh
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# CHECK-LABEL: name: test_shifts_to_revsh
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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- { id: 4, class: gprb }
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- { id: 5, class: gprb }
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- { id: 6, class: gprb }
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- { id: 7, class: gprb }
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- { id: 8, class: gprb }
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- { id: 9, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(s32) = COPY $r0
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; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
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%1(s32) = G_CONSTANT i32 24
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%2(s32) = G_SHL %0(s32), %1(s32)
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%3(s32) = G_CONSTANT i32 16
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%4(s32) = G_ASHR %2(s32), %3(s32)
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%5(s32) = G_CONSTANT i32 8
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%6(s32) = G_LSHR %0(s32), %5(s32)
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%7(s32) = G_CONSTANT 255
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%8(s32) = G_AND %6(s32), %7(s32)
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%9(s32) = G_OR %4(s32), %8(s32)
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; CHECK: [[VREGR:%[0-9]+]]:gpr = REVSH [[VREGX]]
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$r0 = COPY %9(s32)
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; CHECK: $r0 = COPY [[VREGR]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_shifts_to_revsh_commutative
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# CHECK-LABEL: name: test_shifts_to_revsh_commutative
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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- { id: 4, class: gprb }
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- { id: 5, class: gprb }
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- { id: 6, class: gprb }
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- { id: 7, class: gprb }
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- { id: 8, class: gprb }
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- { id: 9, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(s32) = COPY $r0
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; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
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%1(s32) = G_CONSTANT i32 24
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%2(s32) = G_SHL %0(s32), %1(s32)
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%3(s32) = G_CONSTANT i32 16
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%4(s32) = G_ASHR %2(s32), %3(s32)
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%5(s32) = G_CONSTANT i32 8
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%6(s32) = G_LSHR %0(s32), %5(s32)
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%7(s32) = G_CONSTANT 255
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%8(s32) = G_AND %6(s32), %7(s32)
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%9(s32) = G_OR %8(s32), %4(s32)
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; CHECK: [[VREGR:%[0-9]+]]:gpr = REVSH [[VREGX]]
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$r0 = COPY %9(s32)
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; CHECK: $r0 = COPY [[VREGR]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_shifts_no_revsh_features
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# CHECK-LABEL: name: test_shifts_no_revsh
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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- { id: 4, class: gprb }
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- { id: 5, class: gprb }
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- { id: 6, class: gprb }
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- { id: 7, class: gprb }
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- { id: 8, class: gprb }
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- { id: 9, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(s32) = COPY $r0
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%1(s32) = G_CONSTANT i32 24
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%2(s32) = G_SHL %0(s32), %1(s32)
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%3(s32) = G_CONSTANT i32 16
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%4(s32) = G_ASHR %2(s32), %3(s32)
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%5(s32) = G_CONSTANT i32 8
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%6(s32) = G_LSHR %0(s32), %5(s32)
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%7(s32) = G_CONSTANT 255
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%8(s32) = G_AND %6(s32), %7(s32)
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%9(s32) = G_OR %4(s32), %8(s32)
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; We don't really care how this is folded as long as it's not into a REVSH.
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; CHECK-NOT: REVSH
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$r0 = COPY %9(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_shifts_no_revsh_constants
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# CHECK-LABEL: name: test_shifts_no_revsh_constants
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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- { id: 4, class: gprb }
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- { id: 5, class: gprb }
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- { id: 6, class: gprb }
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- { id: 7, class: gprb }
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- { id: 8, class: gprb }
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- { id: 9, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(s32) = COPY $r0
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%1(s32) = G_CONSTANT i32 16 ; REVSH needs 24 here
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%2(s32) = G_SHL %0(s32), %1(s32)
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%3(s32) = G_CONSTANT i32 24 ; REVSH needs 16 here
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%4(s32) = G_ASHR %2(s32), %3(s32)
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%5(s32) = G_CONSTANT i32 8
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%6(s32) = G_LSHR %0(s32), %5(s32)
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%7(s32) = G_CONSTANT 255
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%8(s32) = G_AND %6(s32), %7(s32)
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%9(s32) = G_OR %4(s32), %8(s32)
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; We don't really care how this is folded as long as it's not into a REVSH.
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; CHECK-NOT: REVSH
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$r0 = COPY %9(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_bicrr
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# CHECK-LABEL: name: test_bicrr
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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- { id: 4, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1
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%0(s32) = COPY $r0
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%1(s32) = COPY $r1
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; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
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; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
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%2(s32) = G_CONSTANT i32 -1
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%3(s32) = G_XOR %1, %2
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%4(s32) = G_AND %0, %3
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; CHECK: [[VREGR:%[0-9]+]]:gpr = BICrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
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$r0 = COPY %4(s32)
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; CHECK: $r0 = COPY [[VREGR]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_bicrr_commutative
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# CHECK-LABEL: name: test_bicrr_commutative
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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- { id: 4, class: gprb }
|
|
body: |
|
|
bb.0:
|
|
liveins: $r0, $r1
|
|
|
|
%0(s32) = COPY $r0
|
|
%1(s32) = COPY $r1
|
|
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
|
|
; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
|
|
|
|
%2(s32) = G_CONSTANT i32 -1
|
|
%3(s32) = G_XOR %1, %2
|
|
%4(s32) = G_AND %3, %0
|
|
; CHECK: [[VREGR:%[0-9]+]]:gpr = BICrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
|
|
|
|
$r0 = COPY %4(s32)
|
|
; CHECK: $r0 = COPY [[VREGR]]
|
|
|
|
BX_RET 14, $noreg, implicit $r0
|
|
; CHECK: BX_RET 14, $noreg, implicit $r0
|
|
...
|
|
---
|
|
name: test_bicri
|
|
# CHECK-LABEL: name: test_bicri
|
|
legalized: true
|
|
regBankSelected: true
|
|
selected: false
|
|
# CHECK: selected: true
|
|
registers:
|
|
- { id: 0, class: gprb }
|
|
- { id: 1, class: gprb }
|
|
- { id: 2, class: gprb }
|
|
- { id: 3, class: gprb }
|
|
- { id: 4, class: gprb }
|
|
body: |
|
|
bb.0:
|
|
liveins: $r0
|
|
|
|
%0(s32) = COPY $r0
|
|
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
|
|
|
|
; This test and the following ones are a bit contrived, since they use a
|
|
; G_XOR that can be constant-folded. They exist mostly to validate the
|
|
; TableGen pattern that defines BICri. We also have a pattern for matching a
|
|
; G_AND with a G_CONSTANT operand directly, which is the more common case,
|
|
; but that will be covered by different tests.
|
|
%1(s32) = G_CONSTANT i32 192
|
|
|
|
%2(s32) = G_CONSTANT i32 -1
|
|
%3(s32) = G_XOR %1, %2
|
|
%4(s32) = G_AND %0, %3
|
|
; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, $noreg, $noreg
|
|
|
|
$r0 = COPY %4(s32)
|
|
; CHECK: $r0 = COPY [[VREGR]]
|
|
|
|
BX_RET 14, $noreg, implicit $r0
|
|
; CHECK: BX_RET 14, $noreg, implicit $r0
|
|
...
|
|
---
|
|
name: test_bicri_commutative_xor
|
|
# CHECK-LABEL: name: test_bicri_commutative_xor
|
|
legalized: true
|
|
regBankSelected: true
|
|
selected: false
|
|
# CHECK: selected: true
|
|
registers:
|
|
- { id: 0, class: gprb }
|
|
- { id: 1, class: gprb }
|
|
- { id: 2, class: gprb }
|
|
- { id: 3, class: gprb }
|
|
- { id: 4, class: gprb }
|
|
body: |
|
|
bb.0:
|
|
liveins: $r0
|
|
|
|
%0(s32) = COPY $r0
|
|
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
|
|
|
|
%1(s32) = G_CONSTANT i32 192
|
|
|
|
%2(s32) = G_CONSTANT i32 -1
|
|
%3(s32) = G_XOR %2, %1
|
|
%4(s32) = G_AND %0, %3
|
|
; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, $noreg, $noreg
|
|
|
|
$r0 = COPY %4(s32)
|
|
; CHECK: $r0 = COPY [[VREGR]]
|
|
|
|
BX_RET 14, $noreg, implicit $r0
|
|
; CHECK: BX_RET 14, $noreg, implicit $r0
|
|
...
|
|
---
|
|
name: test_bicri_commutative_and
|
|
# CHECK-LABEL: name: test_bicri_commutative_and
|
|
legalized: true
|
|
regBankSelected: true
|
|
selected: false
|
|
# CHECK: selected: true
|
|
registers:
|
|
- { id: 0, class: gprb }
|
|
- { id: 1, class: gprb }
|
|
- { id: 2, class: gprb }
|
|
- { id: 3, class: gprb }
|
|
- { id: 4, class: gprb }
|
|
body: |
|
|
bb.0:
|
|
liveins: $r0
|
|
|
|
%0(s32) = COPY $r0
|
|
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
|
|
|
|
%1(s32) = G_CONSTANT i32 192
|
|
|
|
%2(s32) = G_CONSTANT i32 -1
|
|
%3(s32) = G_XOR %1, %2
|
|
%4(s32) = G_AND %3, %0
|
|
; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, $noreg, $noreg
|
|
|
|
$r0 = COPY %4(s32)
|
|
; CHECK: $r0 = COPY [[VREGR]]
|
|
|
|
BX_RET 14, $noreg, implicit $r0
|
|
; CHECK: BX_RET 14, $noreg, implicit $r0
|
|
...
|
|
---
|
|
name: test_bicri_commutative_both
|
|
# CHECK-LABEL: name: test_bicri_commutative_both
|
|
legalized: true
|
|
regBankSelected: true
|
|
selected: false
|
|
# CHECK: selected: true
|
|
registers:
|
|
- { id: 0, class: gprb }
|
|
- { id: 1, class: gprb }
|
|
- { id: 2, class: gprb }
|
|
- { id: 3, class: gprb }
|
|
- { id: 4, class: gprb }
|
|
body: |
|
|
bb.0:
|
|
liveins: $r0
|
|
|
|
%0(s32) = COPY $r0
|
|
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
|
|
|
|
%1(s32) = G_CONSTANT i32 192
|
|
|
|
%2(s32) = G_CONSTANT i32 -1
|
|
%3(s32) = G_XOR %2, %1
|
|
%4(s32) = G_AND %3, %0
|
|
; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, $noreg, $noreg
|
|
|
|
$r0 = COPY %4(s32)
|
|
; CHECK: $r0 = COPY [[VREGR]]
|
|
|
|
BX_RET 14, $noreg, implicit $r0
|
|
; CHECK: BX_RET 14, $noreg, implicit $r0
|
|
...
|
|
---
|
|
name: test_pkhbt
|
|
# CHECK-LABEL: name: test_pkhbt
|
|
legalized: true
|
|
regBankSelected: true
|
|
selected: false
|
|
# CHECK: selected: true
|
|
registers:
|
|
- { id: 0, class: gprb }
|
|
- { id: 1, class: gprb }
|
|
- { id: 2, class: gprb }
|
|
- { id: 3, class: gprb }
|
|
- { id: 4, class: gprb }
|
|
- { id: 5, class: gprb }
|
|
- { id: 6, class: gprb }
|
|
- { id: 7, class: gprb }
|
|
- { id: 8, class: gprb }
|
|
body: |
|
|
bb.0:
|
|
liveins: $r0, $r1
|
|
|
|
%0(s32) = COPY $r0
|
|
%1(s32) = COPY $r1
|
|
; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
|
|
; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
|
|
|
|
%2(s32) = G_CONSTANT i32 65535 ; 0xFFFF
|
|
%3(s32) = G_AND %0, %2
|
|
|
|
%4(s32) = G_CONSTANT i32 7
|
|
%5(s32) = G_SHL %1, %4
|
|
%6(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
|
|
%7(s32) = G_AND %5, %6
|
|
|
|
%8(s32) = G_OR %3, %7
|
|
; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 7, 14, $noreg
|
|
|
|
$r0 = COPY %8(s32)
|
|
; CHECK: $r0 = COPY [[VREGR]]
|
|
|
|
BX_RET 14, $noreg, implicit $r0
|
|
; CHECK: BX_RET 14, $noreg, implicit $r0
|
|
...
|
|
---
|
|
name: test_pkhbt_commutative
|
|
# CHECK-LABEL: name: test_pkhbt_commutative
|
|
legalized: true
|
|
regBankSelected: true
|
|
selected: false
|
|
# CHECK: selected: true
|
|
registers:
|
|
- { id: 0, class: gprb }
|
|
- { id: 1, class: gprb }
|
|
- { id: 2, class: gprb }
|
|
- { id: 3, class: gprb }
|
|
- { id: 4, class: gprb }
|
|
- { id: 5, class: gprb }
|
|
- { id: 6, class: gprb }
|
|
- { id: 7, class: gprb }
|
|
- { id: 8, class: gprb }
|
|
body: |
|
|
bb.0:
|
|
liveins: $r0, $r1
|
|
|
|
%0(s32) = COPY $r0
|
|
%1(s32) = COPY $r1
|
|
; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
|
|
; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
|
|
|
|
%2(s32) = G_CONSTANT i32 65535 ; 0xFFFF
|
|
%3(s32) = G_AND %0, %2
|
|
|
|
%4(s32) = G_CONSTANT i32 7
|
|
%5(s32) = G_SHL %1, %4
|
|
%6(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
|
|
%7(s32) = G_AND %5, %6
|
|
|
|
%8(s32) = G_OR %7, %3
|
|
; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 7, 14, $noreg
|
|
|
|
$r0 = COPY %8(s32)
|
|
; CHECK: $r0 = COPY [[VREGR]]
|
|
|
|
BX_RET 14, $noreg, implicit $r0
|
|
; CHECK: BX_RET 14, $noreg, implicit $r0
|
|
...
|
|
---
|
|
name: test_pkhbt_imm16_31
|
|
# CHECK-LABEL: name: test_pkhbt_imm16_31
|
|
legalized: true
|
|
regBankSelected: true
|
|
selected: false
|
|
# CHECK: selected: true
|
|
registers:
|
|
- { id: 0, class: gprb }
|
|
- { id: 1, class: gprb }
|
|
- { id: 2, class: gprb }
|
|
- { id: 3, class: gprb }
|
|
- { id: 4, class: gprb }
|
|
- { id: 5, class: gprb }
|
|
- { id: 6, class: gprb }
|
|
body: |
|
|
bb.0:
|
|
liveins: $r0, $r1
|
|
|
|
%0(s32) = COPY $r0
|
|
%1(s32) = COPY $r1
|
|
; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
|
|
; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
|
|
|
|
%2(s32) = G_CONSTANT i32 65535 ; 0xFFFF
|
|
%3(s32) = G_AND %0, %2
|
|
|
|
%4(s32) = G_CONSTANT i32 17
|
|
%5(s32) = G_SHL %1, %4
|
|
|
|
%6(s32) = G_OR %3, %5
|
|
; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 17, 14, $noreg
|
|
|
|
$r0 = COPY %6(s32)
|
|
; CHECK: $r0 = COPY [[VREGR]]
|
|
|
|
BX_RET 14, $noreg, implicit $r0
|
|
; CHECK: BX_RET 14, $noreg, implicit $r0
|
|
...
|
|
---
|
|
name: test_pkhbt_unshifted
|
|
# CHECK-LABEL: name: test_pkhbt_unshifted
|
|
legalized: true
|
|
regBankSelected: true
|
|
selected: false
|
|
# CHECK: selected: true
|
|
registers:
|
|
- { id: 0, class: gprb }
|
|
- { id: 1, class: gprb }
|
|
- { id: 2, class: gprb }
|
|
- { id: 3, class: gprb }
|
|
- { id: 4, class: gprb }
|
|
- { id: 5, class: gprb }
|
|
- { id: 6, class: gprb }
|
|
body: |
|
|
bb.0:
|
|
liveins: $r0, $r1
|
|
|
|
%0(s32) = COPY $r0
|
|
%1(s32) = COPY $r1
|
|
; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
|
|
; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
|
|
|
|
%2(s32) = G_CONSTANT i32 65535 ; 0xFFFF
|
|
%3(s32) = G_AND %0, %2
|
|
|
|
%4(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
|
|
%5(s32) = G_AND %1, %4
|
|
|
|
%6(s32) = G_OR %3, %5
|
|
; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 0, 14, $noreg
|
|
|
|
$r0 = COPY %6(s32)
|
|
; CHECK: $r0 = COPY [[VREGR]]
|
|
|
|
BX_RET 14, $noreg, implicit $r0
|
|
; CHECK: BX_RET 14, $noreg, implicit $r0
|
|
...
|
|
---
|
|
name: test_pkhtb_imm16
|
|
# CHECK-LABEL: name: test_pkhtb_imm16
|
|
legalized: true
|
|
regBankSelected: true
|
|
selected: false
|
|
# CHECK: selected: true
|
|
registers:
|
|
- { id: 0, class: gprb }
|
|
- { id: 1, class: gprb }
|
|
- { id: 2, class: gprb }
|
|
- { id: 3, class: gprb }
|
|
- { id: 4, class: gprb }
|
|
- { id: 5, class: gprb }
|
|
- { id: 6, class: gprb }
|
|
body: |
|
|
bb.0:
|
|
liveins: $r0, $r1
|
|
|
|
%0(s32) = COPY $r0
|
|
%1(s32) = COPY $r1
|
|
; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
|
|
; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
|
|
|
|
%2(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
|
|
%3(s32) = G_AND %0, %2
|
|
|
|
%4(s32) = G_CONSTANT i32 16
|
|
%5(s32) = G_LSHR %1, %4
|
|
|
|
%6(s32) = G_OR %3, %5
|
|
; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHTB [[VREGX]], [[VREGY]], 16, 14, $noreg
|
|
|
|
$r0 = COPY %6(s32)
|
|
; CHECK: $r0 = COPY [[VREGR]]
|
|
|
|
BX_RET 14, $noreg, implicit $r0
|
|
; CHECK: BX_RET 14, $noreg, implicit $r0
|
|
...
|
|
---
|
|
name: test_pkhtb_imm1_15
|
|
# CHECK-LABEL: name: test_pkhtb_imm1_15
|
|
legalized: true
|
|
regBankSelected: true
|
|
selected: false
|
|
# CHECK: selected: true
|
|
registers:
|
|
- { id: 0, class: gprb }
|
|
- { id: 1, class: gprb }
|
|
- { id: 2, class: gprb }
|
|
- { id: 3, class: gprb }
|
|
- { id: 4, class: gprb }
|
|
- { id: 5, class: gprb }
|
|
- { id: 6, class: gprb }
|
|
- { id: 7, class: gprb }
|
|
- { id: 8, class: gprb }
|
|
body: |
|
|
bb.0:
|
|
liveins: $r0, $r1
|
|
|
|
%0(s32) = COPY $r0
|
|
%1(s32) = COPY $r1
|
|
; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
|
|
; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
|
|
|
|
%2(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
|
|
%3(s32) = G_AND %0, %2
|
|
|
|
%4(s32) = G_CONSTANT i32 7
|
|
%5(s32) = G_LSHR %1, %4
|
|
%6(s32) = G_CONSTANT i32 65535 ; 0xFFFF
|
|
%7(s32) = G_AND %5, %6
|
|
|
|
%8(s32) = G_OR %3, %7
|
|
; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHTB [[VREGX]], [[VREGY]], 7, 14, $noreg
|
|
|
|
$r0 = COPY %8(s32)
|
|
; CHECK: $r0 = COPY [[VREGR]]
|
|
|
|
BX_RET 14, $noreg, implicit $r0
|
|
; CHECK: BX_RET 14, $noreg, implicit $r0
|
|
...
|
|
---
|
|
name: test_movti16_0xffff
|
|
# CHECK-LABEL: name: test_movti16_0xffff
|
|
legalized: true
|
|
regBankSelected: true
|
|
selected: false
|
|
# CHECK: selected: true
|
|
registers:
|
|
- { id: 0, class: gprb }
|
|
- { id: 1, class: gprb }
|
|
- { id: 2, class: gprb }
|
|
body: |
|
|
bb.0:
|
|
liveins: $r0
|
|
|
|
%0(s32) = COPY $r0
|
|
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
|
|
|
|
%1(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
|
|
|
|
%2(s32) = G_OR %0, %1
|
|
; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MOVTi16 [[VREGX]], 65535, 14, $noreg
|
|
|
|
$r0 = COPY %2(s32)
|
|
; CHECK: $r0 = COPY [[VREGR]]
|
|
|
|
BX_RET 14, $noreg, implicit $r0
|
|
; CHECK: BX_RET 14, $noreg, implicit $r0
|
|
...
|
|
---
|
|
name: test_vnmuls
|
|
# CHECK-LABEL: name: test_vnmuls
|
|
legalized: true
|
|
regBankSelected: true
|
|
selected: false
|
|
# CHECK: selected: true
|
|
registers:
|
|
- { id: 0, class: fprb }
|
|
- { id: 1, class: fprb }
|
|
- { id: 2, class: fprb }
|
|
- { id: 3, class: fprb }
|
|
body: |
|
|
bb.0:
|
|
liveins: $s0, $s1
|
|
|
|
%0(s32) = COPY $s0
|
|
%1(s32) = COPY $s1
|
|
; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY $s0
|
|
; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY $s1
|
|
|
|
%2(s32) = G_FMUL %0, %1
|
|
%3(s32) = G_FNEG %2
|
|
; CHECK: [[VREGR:%[0-9]+]]:spr = VNMULS [[VREGX]], [[VREGY]], 14, $noreg
|
|
|
|
$s0 = COPY %3(s32)
|
|
; CHECK: $s0 = COPY [[VREGR]]
|
|
|
|
BX_RET 14, $noreg, implicit $s0
|
|
; CHECK: BX_RET 14, $noreg, implicit $s0
|
|
...
|
|
---
|
|
name: test_vnmuls_reassociate
|
|
# CHECK-LABEL: name: test_vnmuls_reassociate
|
|
legalized: true
|
|
regBankSelected: true
|
|
selected: false
|
|
# CHECK: selected: true
|
|
registers:
|
|
- { id: 0, class: fprb }
|
|
- { id: 1, class: fprb }
|
|
- { id: 2, class: fprb }
|
|
- { id: 3, class: fprb }
|
|
body: |
|
|
bb.0:
|
|
liveins: $s0, $s1
|
|
|
|
%0(s32) = COPY $s0
|
|
%1(s32) = COPY $s1
|
|
; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY $s0
|
|
; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY $s1
|
|
|
|
%2(s32) = G_FNEG %0
|
|
%3(s32) = G_FMUL %1, %2
|
|
; CHECK: [[VREGR:%[0-9]+]]:spr = VNMULS [[VREGX]], [[VREGY]], 14, $noreg
|
|
|
|
$s0 = COPY %3(s32)
|
|
; CHECK: $s0 = COPY [[VREGR]]
|
|
|
|
BX_RET 14, $noreg, implicit $s0
|
|
; CHECK: BX_RET 14, $noreg, implicit $s0
|
|
...
|
|
---
|
|
name: test_vnmuld
|
|
# CHECK-LABEL: name: test_vnmuld
|
|
legalized: true
|
|
regBankSelected: true
|
|
selected: false
|
|
# CHECK: selected: true
|
|
registers:
|
|
- { id: 0, class: fprb }
|
|
- { id: 1, class: fprb }
|
|
- { id: 2, class: fprb }
|
|
- { id: 3, class: fprb }
|
|
body: |
|
|
bb.0:
|
|
liveins: $d0, $d1
|
|
|
|
%0(s64) = COPY $d0
|
|
%1(s64) = COPY $d1
|
|
; CHECK-DAG: [[VREGX:%[0-9]+]]:dpr = COPY $d0
|
|
; CHECK-DAG: [[VREGY:%[0-9]+]]:dpr = COPY $d1
|
|
|
|
%2(s64) = G_FMUL %0, %1
|
|
%3(s64) = G_FNEG %2
|
|
; CHECK: [[VREGR:%[0-9]+]]:dpr = VNMULD [[VREGX]], [[VREGY]], 14, $noreg
|
|
|
|
$d0 = COPY %3(s64)
|
|
; CHECK: $d0 = COPY [[VREGR]]
|
|
|
|
BX_RET 14, $noreg, implicit $d0
|
|
; CHECK: BX_RET 14, $noreg, implicit $d0
|
|
...
|
|
---
|
|
name: test_vfnmas
|
|
# CHECK-LABEL: name: test_vfnmas
|
|
legalized: true
|
|
regBankSelected: true
|
|
selected: false
|
|
# CHECK: selected: true
|
|
registers:
|
|
- { id: 0, class: fprb }
|
|
- { id: 1, class: fprb }
|
|
- { id: 2, class: fprb }
|
|
- { id: 3, class: fprb }
|
|
- { id: 4, class: fprb }
|
|
body: |
|
|
bb.0:
|
|
liveins: $s0, $s1, $s2
|
|
|
|
%0(s32) = COPY $s0
|
|
%1(s32) = COPY $s1
|
|
%2(s32) = COPY $s2
|
|
; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY $s0
|
|
; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY $s1
|
|
; CHECK-DAG: [[VREGZ:%[0-9]+]]:spr = COPY $s2
|
|
|
|
%3(s32) = G_FMA %0, %1, %2
|
|
%4(s32) = G_FNEG %3
|
|
; CHECK: [[VREGR:%[0-9]+]]:spr = VFNMAS [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg
|
|
|
|
$s0 = COPY %4(s32)
|
|
; CHECK: $s0 = COPY [[VREGR]]
|
|
|
|
BX_RET 14, $noreg, implicit $s0
|
|
; CHECK: BX_RET 14, $noreg, implicit $s0
|
|
...
|
|
---
|
|
name: test_vfnmad
|
|
# CHECK-LABEL: name: test_vfnmad
|
|
legalized: true
|
|
regBankSelected: true
|
|
selected: false
|
|
# CHECK: selected: true
|
|
registers:
|
|
- { id: 0, class: fprb }
|
|
- { id: 1, class: fprb }
|
|
- { id: 2, class: fprb }
|
|
- { id: 3, class: fprb }
|
|
- { id: 4, class: fprb }
|
|
- { id: 5, class: fprb }
|
|
body: |
|
|
bb.0:
|
|
liveins: $d0, $d1, $d2
|
|
|
|
%0(s64) = COPY $d0
|
|
%1(s64) = COPY $d1
|
|
%2(s64) = COPY $d2
|
|
; CHECK-DAG: [[VREGX:%[0-9]+]]:dpr = COPY $d0
|
|
; CHECK-DAG: [[VREGY:%[0-9]+]]:dpr = COPY $d1
|
|
; CHECK-DAG: [[VREGZ:%[0-9]+]]:dpr = COPY $d2
|
|
|
|
%3(s64) = G_FNEG %0
|
|
%4(s64) = G_FNEG %2
|
|
%5(s64) = G_FMA %3, %1, %4
|
|
; CHECK: [[VREGR:%[0-9]+]]:dpr = VFNMAD [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg
|
|
|
|
$d0 = COPY %5(s64)
|
|
; CHECK: $d0 = COPY [[VREGR]]
|
|
|
|
BX_RET 14, $noreg, implicit $d0
|
|
; CHECK: BX_RET 14, $noreg, implicit $d0
|
|
...
|
|
---
|
|
name: test_vfmss
|
|
# CHECK-LABEL: name: test_vfmss
|
|
legalized: true
|
|
regBankSelected: true
|
|
selected: false
|
|
# CHECK: selected: true
|
|
registers:
|
|
- { id: 0, class: fprb }
|
|
- { id: 1, class: fprb }
|
|
- { id: 2, class: fprb }
|
|
- { id: 3, class: fprb }
|
|
- { id: 4, class: fprb }
|
|
body: |
|
|
bb.0:
|
|
liveins: $s0, $s1, $s2
|
|
|
|
%0(s32) = COPY $s0
|
|
%1(s32) = COPY $s1
|
|
%2(s32) = COPY $s2
|
|
; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY $s0
|
|
; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY $s1
|
|
; CHECK-DAG: [[VREGZ:%[0-9]+]]:spr = COPY $s2
|
|
|
|
%3(s32) = G_FNEG %0
|
|
%4(s32) = G_FMA %3, %1, %2
|
|
; CHECK: [[VREGR:%[0-9]+]]:spr = VFMSS [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg
|
|
|
|
$s0 = COPY %4(s32)
|
|
; CHECK: $s0 = COPY [[VREGR]]
|
|
|
|
BX_RET 14, $noreg, implicit $s0
|
|
; CHECK: BX_RET 14, $noreg, implicit $s0
|
|
...
|
|
---
|
|
name: test_vfmsd
|
|
# CHECK-LABEL: name: test_vfmsd
|
|
legalized: true
|
|
regBankSelected: true
|
|
selected: false
|
|
# CHECK: selected: true
|
|
registers:
|
|
- { id: 0, class: fprb }
|
|
- { id: 1, class: fprb }
|
|
- { id: 2, class: fprb }
|
|
- { id: 3, class: fprb }
|
|
- { id: 4, class: fprb }
|
|
body: |
|
|
bb.0:
|
|
liveins: $d0, $d1, $d2
|
|
|
|
%0(s64) = COPY $d0
|
|
%1(s64) = COPY $d1
|
|
%2(s64) = COPY $d2
|
|
; CHECK-DAG: [[VREGX:%[0-9]+]]:dpr = COPY $d0
|
|
; CHECK-DAG: [[VREGY:%[0-9]+]]:dpr = COPY $d1
|
|
; CHECK-DAG: [[VREGZ:%[0-9]+]]:dpr = COPY $d2
|
|
|
|
%3(s64) = G_FNEG %1
|
|
%4(s64) = G_FMA %0, %3, %2
|
|
; CHECK: [[VREGR:%[0-9]+]]:dpr = VFMSD [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg
|
|
|
|
$d0 = COPY %4(s64)
|
|
; CHECK: $d0 = COPY [[VREGR]]
|
|
|
|
BX_RET 14, $noreg, implicit $d0
|
|
; CHECK: BX_RET 14, $noreg, implicit $d0
|
|
...
|
|
---
|
|
name: test_vfnmss
|
|
# CHECK-LABEL: name: test_vfnmss
|
|
legalized: true
|
|
regBankSelected: true
|
|
selected: false
|
|
# CHECK: selected: true
|
|
registers:
|
|
- { id: 0, class: fprb }
|
|
- { id: 1, class: fprb }
|
|
- { id: 2, class: fprb }
|
|
- { id: 3, class: fprb }
|
|
- { id: 4, class: fprb }
|
|
body: |
|
|
bb.0:
|
|
liveins: $s0, $s1, $s2
|
|
|
|
%0(s32) = COPY $s0
|
|
%1(s32) = COPY $s1
|
|
%2(s32) = COPY $s2
|
|
; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY $s0
|
|
; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY $s1
|
|
; CHECK-DAG: [[VREGZ:%[0-9]+]]:spr = COPY $s2
|
|
|
|
%3(s32) = G_FNEG %2
|
|
%4(s32) = G_FMA %0, %1, %3
|
|
; CHECK: [[VREGR:%[0-9]+]]:spr = VFNMSS [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg
|
|
|
|
$s0 = COPY %4(s32)
|
|
; CHECK: $s0 = COPY [[VREGR]]
|
|
|
|
BX_RET 14, $noreg, implicit $s0
|
|
; CHECK: BX_RET 14, $noreg, implicit $s0
|
|
...
|