forked from OSchip/llvm-project
fda53373f2
Summary: This currently sets the shift amount RHS to the same type as the LHS, and assumes that the LHS is a simple type. This isn't currently the case e.g. with weird integers sizes, but will eventually be true and will assert if not. That's what you get for having an experimental backend: break it and you get to keep both pieces. Most backends either set the RHS to MVT::i32 or MVT::i64, but WebAssembly is a virtual ISA and tries to have regular-looking binary operations where both operands are the same type (even if a 64-bit RHS shifter is slightly silly, hey it's free!). Subscribers: llvm-commits, sunfish, jfb Differential Revision: http://reviews.llvm.org/D11715 llvm-svn: 243860 |
||
---|---|---|
.. | ||
InstPrinter | ||
MCTargetDesc | ||
TargetInfo | ||
CMakeLists.txt | ||
LLVMBuild.txt | ||
Makefile | ||
README.txt | ||
WebAssembly.h | ||
WebAssembly.td | ||
WebAssemblyAsmPrinter.cpp | ||
WebAssemblyFrameLowering.cpp | ||
WebAssemblyFrameLowering.h | ||
WebAssemblyISelDAGToDAG.cpp | ||
WebAssemblyISelLowering.cpp | ||
WebAssemblyISelLowering.h | ||
WebAssemblyInstrAtomics.td | ||
WebAssemblyInstrCall.td | ||
WebAssemblyInstrControl.td | ||
WebAssemblyInstrConv.td | ||
WebAssemblyInstrFloat.td | ||
WebAssemblyInstrFormats.td | ||
WebAssemblyInstrInfo.cpp | ||
WebAssemblyInstrInfo.h | ||
WebAssemblyInstrInfo.td | ||
WebAssemblyInstrInteger.td | ||
WebAssemblyInstrMemory.td | ||
WebAssemblyInstrSIMD.td | ||
WebAssemblyMachineFunctionInfo.cpp | ||
WebAssemblyMachineFunctionInfo.h | ||
WebAssemblyRegisterInfo.cpp | ||
WebAssemblyRegisterInfo.h | ||
WebAssemblyRegisterInfo.td | ||
WebAssemblySelectionDAGInfo.cpp | ||
WebAssemblySelectionDAGInfo.h | ||
WebAssemblySubtarget.cpp | ||
WebAssemblySubtarget.h | ||
WebAssemblyTargetMachine.cpp | ||
WebAssemblyTargetMachine.h | ||
WebAssemblyTargetObjectFile.h | ||
WebAssemblyTargetTransformInfo.cpp | ||
WebAssemblyTargetTransformInfo.h |
README.txt
//===-- README.txt - Notes for WebAssembly code gen -----------------------===// This WebAssembly backend is presently in a very early stage of development. The code should build and not break anything else, but don't expect a lot more at this point. For more information on WebAssembly itself, see the design documents: * https://github.com/WebAssembly/design/blob/master/README.md The following documents contain some information on the planned semantics and binary encoding of WebAssembly itself: * https://github.com/WebAssembly/design/blob/master/AstSemantics.md * https://github.com/WebAssembly/design/blob/master/BinaryEncoding.md Interesting work that remains to be done: * Write a pass to restructurize irreducible control flow. This needs to be done before register allocation to be efficient, because it may duplicate basic blocks and WebAssembly performs register allocation at a whole-function level. Note that LLVM's GPU code has such a pass, but it linearizes control flow (e.g. both sides of branches execute and are masked) which is undesirable for WebAssembly. * Basic relooper to expose control flow as an AST. * Figure out how to properly use MC for virtual ISAs. This may require some refactoring of MC. //===---------------------------------------------------------------------===//