forked from OSchip/llvm-project
226 lines
7.3 KiB
C++
226 lines
7.3 KiB
C++
//===-- Mips16ISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Mips16 ----===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Subclass of MipsDAGToDAGISel specialized for mips16.
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//
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//===----------------------------------------------------------------------===//
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#include "Mips16ISelDAGToDAG.h"
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#include "MCTargetDesc/MipsBaseInfo.h"
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#include "Mips.h"
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#include "MipsMachineFunction.h"
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#include "MipsRegisterInfo.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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#include "llvm/IR/CFG.h"
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#include "llvm/IR/GlobalValue.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/IR/Type.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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#define DEBUG_TYPE "mips-isel"
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bool Mips16DAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
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Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
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if (!Subtarget->inMips16Mode())
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return false;
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return MipsDAGToDAGISel::runOnMachineFunction(MF);
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}
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/// Select multiply instructions.
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std::pair<SDNode *, SDNode *>
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Mips16DAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, const SDLoc &DL, EVT Ty,
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bool HasLo, bool HasHi) {
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SDNode *Lo = nullptr, *Hi = nullptr;
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SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0),
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N->getOperand(1));
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SDValue InFlag = SDValue(Mul, 0);
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if (HasLo) {
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unsigned Opcode = Mips::Mflo16;
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Lo = CurDAG->getMachineNode(Opcode, DL, Ty, MVT::Glue, InFlag);
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InFlag = SDValue(Lo, 1);
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}
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if (HasHi) {
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unsigned Opcode = Mips::Mfhi16;
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Hi = CurDAG->getMachineNode(Opcode, DL, Ty, InFlag);
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}
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return std::make_pair(Lo, Hi);
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}
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void Mips16DAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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if (!MipsFI->globalBaseRegSet())
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return;
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MachineBasicBlock &MBB = MF.front();
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MachineBasicBlock::iterator I = MBB.begin();
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MachineRegisterInfo &RegInfo = MF.getRegInfo();
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const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
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DebugLoc DL;
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Register V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg(MF);
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const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass;
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V0 = RegInfo.createVirtualRegister(RC);
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V1 = RegInfo.createVirtualRegister(RC);
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V2 = RegInfo.createVirtualRegister(RC);
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BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmX16), V0)
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.addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI);
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BuildMI(MBB, I, DL, TII.get(Mips::AddiuRxPcImmX16), V1)
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.addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO);
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BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
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BuildMI(MBB, I, DL, TII.get(Mips::AdduRxRyRz16), GlobalBaseReg)
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.addReg(V1)
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.addReg(V2);
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}
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void Mips16DAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
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initGlobalBaseReg(MF);
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}
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bool Mips16DAGToDAGISel::selectAddr(bool SPAllowed, SDValue Addr, SDValue &Base,
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SDValue &Offset) {
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SDLoc DL(Addr);
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EVT ValTy = Addr.getValueType();
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// if Address is FI, get the TargetFrameIndex.
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if (SPAllowed) {
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
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Offset = CurDAG->getTargetConstant(0, DL, ValTy);
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return true;
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}
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}
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// on PIC code Load GA
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if (Addr.getOpcode() == MipsISD::Wrapper) {
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Base = Addr.getOperand(0);
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Offset = Addr.getOperand(1);
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return true;
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}
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if (!TM.isPositionIndependent()) {
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if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress))
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return false;
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}
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// Addresses of the form FI+const or FI|const
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if (CurDAG->isBaseWithConstantOffset(Addr)) {
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ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
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if (isInt<16>(CN->getSExtValue())) {
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// If the first operand is a FI, get the TargetFI Node
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if (SPAllowed) {
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if (FrameIndexSDNode *FIN =
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dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
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Offset = CurDAG->getTargetConstant(CN->getZExtValue(), DL, ValTy);
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return true;
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}
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}
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Base = Addr.getOperand(0);
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Offset = CurDAG->getTargetConstant(CN->getZExtValue(), DL, ValTy);
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return true;
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}
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}
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// Operand is a result from an ADD.
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if (Addr.getOpcode() == ISD::ADD) {
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// When loading from constant pools, load the lower address part in
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// the instruction itself. Example, instead of:
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// lui $2, %hi($CPI1_0)
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// addiu $2, $2, %lo($CPI1_0)
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// lwc1 $f0, 0($2)
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// Generate:
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// lui $2, %hi($CPI1_0)
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// lwc1 $f0, %lo($CPI1_0)($2)
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if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
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Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
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SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
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if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
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isa<JumpTableSDNode>(Opnd0)) {
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Base = Addr.getOperand(0);
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Offset = Opnd0;
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return true;
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}
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}
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}
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Base = Addr;
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Offset = CurDAG->getTargetConstant(0, DL, ValTy);
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return true;
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}
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bool Mips16DAGToDAGISel::selectAddr16(SDValue Addr, SDValue &Base,
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SDValue &Offset) {
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return selectAddr(false, Addr, Base, Offset);
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}
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bool Mips16DAGToDAGISel::selectAddr16SP(SDValue Addr, SDValue &Base,
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SDValue &Offset) {
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return selectAddr(true, Addr, Base, Offset);
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}
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/// Select instructions not customized! Used for
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/// expanded, promoted and normal instructions
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bool Mips16DAGToDAGISel::trySelect(SDNode *Node) {
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unsigned Opcode = Node->getOpcode();
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SDLoc DL(Node);
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///
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// Instruction Selection not handled by the auto-generated
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// tablegen selection should be handled here.
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///
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EVT NodeTy = Node->getValueType(0);
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unsigned MultOpc;
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switch (Opcode) {
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default:
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break;
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/// Mul with two results
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case ISD::SMUL_LOHI:
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case ISD::UMUL_LOHI: {
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MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MultuRxRy16 : Mips::MultRxRy16);
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std::pair<SDNode *, SDNode *> LoHi =
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selectMULT(Node, MultOpc, DL, NodeTy, true, true);
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if (!SDValue(Node, 0).use_empty())
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ReplaceUses(SDValue(Node, 0), SDValue(LoHi.first, 0));
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if (!SDValue(Node, 1).use_empty())
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ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0));
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CurDAG->RemoveDeadNode(Node);
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return true;
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}
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case ISD::MULHS:
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case ISD::MULHU: {
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MultOpc = (Opcode == ISD::MULHU ? Mips::MultuRxRy16 : Mips::MultRxRy16);
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auto LoHi = selectMULT(Node, MultOpc, DL, NodeTy, false, true);
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ReplaceNode(Node, LoHi.second);
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return true;
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}
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}
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return false;
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}
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FunctionPass *llvm::createMips16ISelDag(MipsTargetMachine &TM,
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CodeGenOpt::Level OptLevel) {
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return new Mips16DAGToDAGISel(TM, OptLevel);
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}
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