forked from OSchip/llvm-project
246 lines
8.5 KiB
C++
246 lines
8.5 KiB
C++
//===- AArch64TargetTransformInfo.h - AArch64 specific TTI ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file a TargetTransformInfo::Concept conforming object specific to the
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/// AArch64 target machine. It uses the target's detailed information to
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/// provide more precise answers to certain TTI queries, while letting the
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/// target independent and default TTI implementations handle the rest.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
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#define LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
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#include "AArch64.h"
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#include "AArch64Subtarget.h"
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#include "AArch64TargetMachine.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Intrinsics.h"
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#include <cstdint>
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namespace llvm {
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class APInt;
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class Instruction;
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class IntrinsicInst;
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class Loop;
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class SCEV;
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class ScalarEvolution;
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class Type;
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class Value;
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class VectorType;
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class AArch64TTIImpl : public BasicTTIImplBase<AArch64TTIImpl> {
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using BaseT = BasicTTIImplBase<AArch64TTIImpl>;
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using TTI = TargetTransformInfo;
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friend BaseT;
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const AArch64Subtarget *ST;
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const AArch64TargetLowering *TLI;
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const AArch64Subtarget *getST() const { return ST; }
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const AArch64TargetLowering *getTLI() const { return TLI; }
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enum MemIntrinsicType {
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VECTOR_LDST_TWO_ELEMENTS,
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VECTOR_LDST_THREE_ELEMENTS,
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VECTOR_LDST_FOUR_ELEMENTS
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};
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bool isWideningInstruction(Type *Ty, unsigned Opcode,
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ArrayRef<const Value *> Args);
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public:
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explicit AArch64TTIImpl(const AArch64TargetMachine *TM, const Function &F)
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: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
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TLI(ST->getTargetLowering()) {}
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bool areInlineCompatible(const Function *Caller,
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const Function *Callee) const;
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/// \name Scalar TTI Implementations
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/// @{
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using BaseT::getIntImmCost;
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int getIntImmCost(int64_t Val);
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int getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind);
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int getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm,
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Type *Ty, TTI::TargetCostKind CostKind,
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Instruction *Inst = nullptr);
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int getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
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Type *Ty, TTI::TargetCostKind CostKind);
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TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth);
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/// @}
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/// \name Vector TTI Implementations
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/// @{
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bool enableInterleavedAccessVectorization() { return true; }
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unsigned getNumberOfRegisters(unsigned ClassID) const {
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bool Vector = (ClassID == 1);
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if (Vector) {
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if (ST->hasNEON())
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return 32;
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return 0;
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}
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return 31;
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}
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unsigned getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
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TTI::TargetCostKind CostKind);
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unsigned getRegisterBitWidth(bool Vector) const {
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if (Vector) {
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if (ST->hasSVE())
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return std::max(ST->getMinSVEVectorSizeInBits(), 128u);
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if (ST->hasNEON())
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return 128;
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return 0;
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}
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return 64;
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}
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unsigned getMinVectorRegisterBitWidth() {
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return ST->getMinVectorRegisterBitWidth();
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}
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unsigned getMaxInterleaveFactor(unsigned VF);
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int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
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TTI::CastContextHint CCH, TTI::TargetCostKind CostKind,
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const Instruction *I = nullptr);
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int getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy,
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unsigned Index);
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unsigned getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind);
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int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
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int getArithmeticInstrCost(
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unsigned Opcode, Type *Ty,
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TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput,
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TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
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TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
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TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
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TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None,
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ArrayRef<const Value *> Args = ArrayRef<const Value *>(),
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const Instruction *CxtI = nullptr);
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int getAddressComputationCost(Type *Ty, ScalarEvolution *SE, const SCEV *Ptr);
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int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
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CmpInst::Predicate VecPred,
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TTI::TargetCostKind CostKind,
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const Instruction *I = nullptr);
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TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize,
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bool IsZeroCmp) const;
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bool useNeonVector(const Type *Ty) const;
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int getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment,
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unsigned AddressSpace,
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TTI::TargetCostKind CostKind,
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const Instruction *I = nullptr);
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int getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys);
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void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::UnrollingPreferences &UP);
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void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::PeelingPreferences &PP);
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Value *getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst,
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Type *ExpectedType);
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bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info);
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bool isLegalMaskedLoadStore(Type *DataType, Align Alignment) {
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if (!isa<ScalableVectorType>(DataType) || !ST->hasSVE())
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return false;
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Type *Ty = cast<ScalableVectorType>(DataType)->getElementType();
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if (Ty->isPointerTy())
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return true;
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if (Ty->isBFloatTy() || Ty->isHalfTy() ||
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Ty->isFloatTy() || Ty->isDoubleTy())
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return true;
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if (Ty->isIntegerTy(8) || Ty->isIntegerTy(16) ||
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Ty->isIntegerTy(32) || Ty->isIntegerTy(64))
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return true;
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return false;
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}
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bool isLegalMaskedLoad(Type *DataType, Align Alignment) {
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return isLegalMaskedLoadStore(DataType, Alignment);
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}
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bool isLegalMaskedStore(Type *DataType, Align Alignment) {
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return isLegalMaskedLoadStore(DataType, Alignment);
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}
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bool isLegalNTStore(Type *DataType, Align Alignment) {
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// NOTE: The logic below is mostly geared towards LV, which calls it with
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// vectors with 2 elements. We might want to improve that, if other
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// users show up.
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// Nontemporal vector stores can be directly lowered to STNP, if the vector
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// can be halved so that each half fits into a register. That's the case if
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// the element type fits into a register and the number of elements is a
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// power of 2 > 1.
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if (auto *DataTypeVTy = dyn_cast<VectorType>(DataType)) {
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unsigned NumElements =
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cast<FixedVectorType>(DataTypeVTy)->getNumElements();
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unsigned EltSize = DataTypeVTy->getElementType()->getScalarSizeInBits();
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return NumElements > 1 && isPowerOf2_64(NumElements) && EltSize >= 8 &&
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EltSize <= 128 && isPowerOf2_64(EltSize);
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}
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return BaseT::isLegalNTStore(DataType, Alignment);
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}
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int getInterleavedMemoryOpCost(
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unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
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Align Alignment, unsigned AddressSpace,
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TTI::TargetCostKind CostKind = TTI::TCK_SizeAndLatency,
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bool UseMaskForCond = false, bool UseMaskForGaps = false);
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bool
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shouldConsiderAddressTypePromotion(const Instruction &I,
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bool &AllowPromotionWithoutCommonHeader);
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bool shouldExpandReduction(const IntrinsicInst *II) const { return false; }
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unsigned getGISelRematGlobalCost() const {
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return 2;
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}
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bool useReductionIntrinsic(unsigned Opcode, Type *Ty,
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TTI::ReductionFlags Flags) const;
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int getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
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bool IsPairwiseForm,
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TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput);
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int getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, int Index,
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VectorType *SubTp);
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/// @}
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
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