forked from OSchip/llvm-project
718 lines
27 KiB
TableGen
718 lines
27 KiB
TableGen
//===-- VOP2Instructions.td - Vector Instruction Defintions ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// VOP2 Classes
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//===----------------------------------------------------------------------===//
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class VOP2e <bits<6> op, VOPProfile P> : Enc32 {
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bits<8> vdst;
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bits<9> src0;
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bits<8> src1;
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let Inst{8-0} = !if(P.HasSrc0, src0, 0);
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let Inst{16-9} = !if(P.HasSrc1, src1, 0);
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let Inst{24-17} = !if(P.EmitDst, vdst, 0);
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let Inst{30-25} = op;
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let Inst{31} = 0x0; //encoding
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}
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class VOP2_MADKe <bits<6> op, VOPProfile P> : Enc64 {
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bits<8> vdst;
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bits<9> src0;
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bits<8> src1;
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bits<32> imm;
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let Inst{8-0} = !if(P.HasSrc0, src0, 0);
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let Inst{16-9} = !if(P.HasSrc1, src1, 0);
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let Inst{24-17} = !if(P.EmitDst, vdst, 0);
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let Inst{30-25} = op;
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let Inst{31} = 0x0; // encoding
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let Inst{63-32} = imm;
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}
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class VOP2_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], string suffix = "_e32"> :
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InstSI <P.Outs32, P.Ins32, "", pattern>,
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VOP <opName>,
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SIMCInstr <opName#suffix, SIEncodingFamily.NONE>,
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MnemonicAlias<opName#suffix, opName> {
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let isPseudo = 1;
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let isCodeGenOnly = 1;
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let UseNamedOperandTable = 1;
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string Mnemonic = opName;
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string AsmOperands = P.Asm32;
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let Size = 4;
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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let SubtargetPredicate = isGCN;
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let VOP2 = 1;
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let VALU = 1;
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let Uses = [EXEC];
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let AsmVariantName = AMDGPUAsmVariants.Default;
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VOPProfile Pfl = P;
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}
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class VOP2_Real <VOP2_Pseudo ps, int EncodingFamily> :
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InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
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SIMCInstr <ps.PseudoInstr, EncodingFamily> {
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let isPseudo = 0;
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let isCodeGenOnly = 0;
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// copy relevant pseudo op flags
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let SubtargetPredicate = ps.SubtargetPredicate;
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let AsmMatchConverter = ps.AsmMatchConverter;
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let AsmVariantName = ps.AsmVariantName;
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let Constraints = ps.Constraints;
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let DisableEncoding = ps.DisableEncoding;
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let TSFlags = ps.TSFlags;
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}
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class getVOP2Pat64 <SDPatternOperator node, VOPProfile P> : LetDummies {
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list<dag> ret = !if(P.HasModifiers,
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[(set P.DstVT:$vdst,
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(node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
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(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
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[(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]);
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}
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multiclass VOP2Inst <string opName,
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VOPProfile P,
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SDPatternOperator node = null_frag,
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string revOp = opName> {
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def _e32 : VOP2_Pseudo <opName, P>,
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Commutable_REV<revOp#"_e32", !eq(revOp, opName)>;
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def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
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Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
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}
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multiclass VOP2bInst <string opName,
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VOPProfile P,
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SDPatternOperator node = null_frag,
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string revOp = opName,
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bit useSGPRInput = !eq(P.NumSrcArgs, 3)> {
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let SchedRW = [Write32Bit, WriteSALU] in {
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let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC] in {
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def _e32 : VOP2_Pseudo <opName, P>,
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Commutable_REV<revOp#"_e32", !eq(revOp, opName)>;
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}
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def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
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Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
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}
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}
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multiclass VOP2eInst <string opName,
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VOPProfile P,
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SDPatternOperator node = null_frag,
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string revOp = opName,
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bit useSGPRInput = !eq(P.NumSrcArgs, 3)> {
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let SchedRW = [Write32Bit] in {
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let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]) in {
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def _e32 : VOP2_Pseudo <opName, P>,
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Commutable_REV<revOp#"_e32", !eq(revOp, opName)>;
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}
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def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
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Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
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}
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}
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class VOP_MADAK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {
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field dag Ins32 = (ins VCSrc_f32:$src0, VGPR_32:$src1, f32kimm:$imm);
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field string Asm32 = "$vdst, $src0, $src1, $imm";
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field bit HasExt = 0;
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}
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def VOP_MADAK_F16 : VOP_MADAK <f16>;
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def VOP_MADAK_F32 : VOP_MADAK <f32>;
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class VOP_MADMK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {
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field dag Ins32 = (ins VCSrc_f32:$src0, f32kimm:$imm, VGPR_32:$src1);
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field string Asm32 = "$vdst, $src0, $imm, $src1";
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field bit HasExt = 0;
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}
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def VOP_MADMK_F16 : VOP_MADMK <f16>;
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def VOP_MADMK_F32 : VOP_MADMK <f32>;
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class VOP_MAC <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {
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let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VGPR_32:$src2);
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let Ins64 = getIns64<Src0RC64, Src1RC64, RegisterOperand<VGPR_32>, 3,
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HasModifiers, Src0Mod, Src1Mod, Src2Mod>.ret;
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let InsDPP = (ins FP32InputMods:$src0_modifiers, Src0RC32:$src0,
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FP32InputMods:$src1_modifiers, Src1RC32:$src1,
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VGPR_32:$src2, // stub argument
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dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
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bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
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let InsSDWA = (ins FP32InputMods:$src0_modifiers, Src0RC32:$src0,
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FP32InputMods:$src1_modifiers, Src1RC32:$src1,
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VGPR_32:$src2, // stub argument
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clampmod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused,
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src0_sel:$src0_sel, src1_sel:$src1_sel);
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let Asm32 = getAsm32<1, 2, vt>.ret;
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let AsmDPP = getAsmDPP<1, 2, HasModifiers, vt>.ret;
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let AsmSDWA = getAsmSDWA<1, 2, HasModifiers, vt>.ret;
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let HasSrc2 = 0;
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let HasSrc2Mods = 0;
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let HasExt = 1;
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}
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def VOP_MAC_F16 : VOP_MAC <f16> {
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// FIXME: Move 'Asm64' definition to VOP_MAC, and use 'vt'. Currently it gives
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// 'not a string initializer' error.
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let Asm64 = getAsm64<1, 2, HasModifiers, f16>.ret;
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}
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def VOP_MAC_F32 : VOP_MAC <f32> {
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// FIXME: Move 'Asm64' definition to VOP_MAC, and use 'vt'. Currently it gives
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// 'not a string initializer' error.
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let Asm64 = getAsm64<1, 2, HasModifiers, f32>.ret;
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}
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// Write out to vcc or arbitrary SGPR.
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def VOP2b_I32_I1_I32_I32 : VOPProfile<[i32, i32, i32, untyped]> {
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let Asm32 = "$vdst, vcc, $src0, $src1";
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let Asm64 = "$vdst, $sdst, $src0, $src1";
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let Outs32 = (outs DstRC:$vdst);
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let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
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}
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// Write out to vcc or arbitrary SGPR and read in from vcc or
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// arbitrary SGPR.
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def VOP2b_I32_I1_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1]> {
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// We use VCSrc_b32 to exclude literal constants, even though the
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// encoding normally allows them since the implicit VCC use means
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// using one would always violate the constant bus
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// restriction. SGPRs are still allowed because it should
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// technically be possible to use VCC again as src0.
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let Src0RC32 = VCSrc_b32;
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let Asm32 = "$vdst, vcc, $src0, $src1, vcc";
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let Asm64 = "$vdst, $sdst, $src0, $src1, $src2";
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let Outs32 = (outs DstRC:$vdst);
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let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
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// Suppress src2 implied by type since the 32-bit encoding uses an
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// implicit VCC use.
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let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
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}
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// Read in from vcc or arbitrary SGPR
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def VOP2e_I32_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1]> {
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let Src0RC32 = VCSrc_b32; // See comment in def VOP2b_I32_I1_I32_I32_I1 above.
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let Asm32 = "$vdst, $src0, $src1, vcc";
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let Asm64 = "$vdst, $src0, $src1, $src2";
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let Outs32 = (outs DstRC:$vdst);
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let Outs64 = (outs DstRC:$vdst);
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// Suppress src2 implied by type since the 32-bit encoding uses an
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// implicit VCC use.
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let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
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}
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def VOP_READLANE : VOPProfile<[i32, i32, i32]> {
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let Outs32 = (outs SReg_32:$vdst);
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let Outs64 = Outs32;
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let Ins32 = (ins VGPR_32:$src0, SCSrc_b32:$src1);
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let Ins64 = Ins32;
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let Asm32 = " $vdst, $src0, $src1";
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let Asm64 = Asm32;
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}
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def VOP_WRITELANE : VOPProfile<[i32, i32, i32]> {
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let Outs32 = (outs VGPR_32:$vdst);
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let Outs64 = Outs32;
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let Ins32 = (ins SReg_32:$src0, SCSrc_b32:$src1);
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let Ins64 = Ins32;
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let Asm32 = " $vdst, $src0, $src1";
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let Asm64 = Asm32;
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}
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//===----------------------------------------------------------------------===//
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// VOP2 Instructions
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//===----------------------------------------------------------------------===//
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let SubtargetPredicate = isGCN in {
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defm V_CNDMASK_B32 : VOP2eInst <"v_cndmask_b32", VOP2e_I32_I32_I32_I1>;
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def V_MADMK_F32 : VOP2_Pseudo <"v_madmk_f32", VOP_MADMK_F32>;
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let isCommutable = 1 in {
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defm V_ADD_F32 : VOP2Inst <"v_add_f32", VOP_F32_F32_F32, fadd>;
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defm V_SUB_F32 : VOP2Inst <"v_sub_f32", VOP_F32_F32_F32, fsub>;
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defm V_SUBREV_F32 : VOP2Inst <"v_subrev_f32", VOP_F32_F32_F32, null_frag, "v_sub_f32">;
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defm V_MUL_LEGACY_F32 : VOP2Inst <"v_mul_legacy_f32", VOP_F32_F32_F32, AMDGPUfmul_legacy>;
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defm V_MUL_F32 : VOP2Inst <"v_mul_f32", VOP_F32_F32_F32, fmul>;
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defm V_MUL_I32_I24 : VOP2Inst <"v_mul_i32_i24", VOP_I32_I32_I32, AMDGPUmul_i24>;
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defm V_MUL_HI_I32_I24 : VOP2Inst <"v_mul_hi_i32_i24", VOP_I32_I32_I32, AMDGPUmulhi_i24>;
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defm V_MUL_U32_U24 : VOP2Inst <"v_mul_u32_u24", VOP_I32_I32_I32, AMDGPUmul_u24>;
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defm V_MUL_HI_U32_U24 : VOP2Inst <"v_mul_hi_u32_u24", VOP_I32_I32_I32, AMDGPUmulhi_u24>;
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defm V_MIN_F32 : VOP2Inst <"v_min_f32", VOP_F32_F32_F32, fminnum>;
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defm V_MAX_F32 : VOP2Inst <"v_max_f32", VOP_F32_F32_F32, fmaxnum>;
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defm V_MIN_I32 : VOP2Inst <"v_min_i32", VOP_I32_I32_I32>;
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defm V_MAX_I32 : VOP2Inst <"v_max_i32", VOP_I32_I32_I32>;
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defm V_MIN_U32 : VOP2Inst <"v_min_u32", VOP_I32_I32_I32>;
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defm V_MAX_U32 : VOP2Inst <"v_max_u32", VOP_I32_I32_I32>;
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defm V_LSHRREV_B32 : VOP2Inst <"v_lshrrev_b32", VOP_I32_I32_I32, null_frag, "v_lshr_b32">;
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defm V_ASHRREV_I32 : VOP2Inst <"v_ashrrev_i32", VOP_I32_I32_I32, null_frag, "v_ashr_i32">;
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defm V_LSHLREV_B32 : VOP2Inst <"v_lshlrev_b32", VOP_I32_I32_I32, null_frag, "v_lshl_b32">;
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defm V_AND_B32 : VOP2Inst <"v_and_b32", VOP_I32_I32_I32>;
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defm V_OR_B32 : VOP2Inst <"v_or_b32", VOP_I32_I32_I32>;
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defm V_XOR_B32 : VOP2Inst <"v_xor_b32", VOP_I32_I32_I32>;
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let Constraints = "$vdst = $src2", DisableEncoding="$src2",
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isConvertibleToThreeAddress = 1 in {
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defm V_MAC_F32 : VOP2Inst <"v_mac_f32", VOP_MAC_F32>;
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}
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def V_MADAK_F32 : VOP2_Pseudo <"v_madak_f32", VOP_MADAK_F32>;
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// No patterns so that the scalar instructions are always selected.
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// The scalar versions will be replaced with vector when needed later.
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// V_ADD_I32, V_SUB_I32, and V_SUBREV_I32 where renamed to *_U32 in VI,
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// but the VI instructions behave the same as the SI versions.
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defm V_ADD_I32 : VOP2bInst <"v_add_i32", VOP2b_I32_I1_I32_I32>;
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defm V_SUB_I32 : VOP2bInst <"v_sub_i32", VOP2b_I32_I1_I32_I32>;
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defm V_SUBREV_I32 : VOP2bInst <"v_subrev_i32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_i32">;
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defm V_ADDC_U32 : VOP2bInst <"v_addc_u32", VOP2b_I32_I1_I32_I32_I1>;
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defm V_SUBB_U32 : VOP2bInst <"v_subb_u32", VOP2b_I32_I1_I32_I32_I1>;
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defm V_SUBBREV_U32 : VOP2bInst <"v_subbrev_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32">;
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} // End isCommutable = 1
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// These are special and do not read the exec mask.
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let isConvergent = 1, Uses = []<Register> in {
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def V_READLANE_B32 : VOP2_Pseudo<"v_readlane_b32", VOP_READLANE,
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[(set i32:$vdst, (int_amdgcn_readlane i32:$src0, i32:$src1))], "">;
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def V_WRITELANE_B32 : VOP2_Pseudo<"v_writelane_b32", VOP_WRITELANE, [], "">;
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} // End isConvergent = 1
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defm V_BFM_B32 : VOP2Inst <"v_bfm_b32", VOP_I32_I32_I32>;
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defm V_BCNT_U32_B32 : VOP2Inst <"v_bcnt_u32_b32", VOP_I32_I32_I32>;
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defm V_MBCNT_LO_U32_B32 : VOP2Inst <"v_mbcnt_lo_u32_b32", VOP_I32_I32_I32, int_amdgcn_mbcnt_lo>;
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defm V_MBCNT_HI_U32_B32 : VOP2Inst <"v_mbcnt_hi_u32_b32", VOP_I32_I32_I32, int_amdgcn_mbcnt_hi>;
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defm V_LDEXP_F32 : VOP2Inst <"v_ldexp_f32", VOP_F32_F32_I32, AMDGPUldexp>;
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defm V_CVT_PKACCUM_U8_F32 : VOP2Inst <"v_cvt_pkaccum_u8_f32", VOP_I32_F32_I32>; // TODO: set "Uses = dst"
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defm V_CVT_PKNORM_I16_F32 : VOP2Inst <"v_cvt_pknorm_i16_f32", VOP_I32_F32_F32>;
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defm V_CVT_PKNORM_U16_F32 : VOP2Inst <"v_cvt_pknorm_u16_f32", VOP_I32_F32_F32>;
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defm V_CVT_PKRTZ_F16_F32 : VOP2Inst <"v_cvt_pkrtz_f16_f32", VOP_I32_F32_F32, int_SI_packf16>;
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defm V_CVT_PK_U16_U32 : VOP2Inst <"v_cvt_pk_u16_u32", VOP_I32_I32_I32>;
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defm V_CVT_PK_I16_I32 : VOP2Inst <"v_cvt_pk_i16_i32", VOP_I32_I32_I32>;
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} // End SubtargetPredicate = isGCN
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// These instructions only exist on SI and CI
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let SubtargetPredicate = isSICI in {
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defm V_MIN_LEGACY_F32 : VOP2Inst <"v_min_legacy_f32", VOP_F32_F32_F32, AMDGPUfmin_legacy>;
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defm V_MAX_LEGACY_F32 : VOP2Inst <"v_max_legacy_f32", VOP_F32_F32_F32, AMDGPUfmax_legacy>;
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let isCommutable = 1 in {
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defm V_MAC_LEGACY_F32 : VOP2Inst <"v_mac_legacy_f32", VOP_F32_F32_F32>;
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defm V_LSHR_B32 : VOP2Inst <"v_lshr_b32", VOP_I32_I32_I32>;
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defm V_ASHR_I32 : VOP2Inst <"v_ashr_i32", VOP_I32_I32_I32>;
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defm V_LSHL_B32 : VOP2Inst <"v_lshl_b32", VOP_I32_I32_I32>;
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} // End isCommutable = 1
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} // End let SubtargetPredicate = SICI
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let SubtargetPredicate = isVI in {
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def V_MADMK_F16 : VOP2_Pseudo <"v_madmk_f16", VOP_MADMK_F16>;
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defm V_LSHLREV_B16 : VOP2Inst <"v_lshlrev_b16", VOP_I16_I16_I16>;
|
|
defm V_LSHRREV_B16 : VOP2Inst <"v_lshrrev_b16", VOP_I16_I16_I16>;
|
|
defm V_ASHRREV_B16 : VOP2Inst <"v_ashrrev_b16", VOP_I16_I16_I16>;
|
|
defm V_LDEXP_F16 : VOP2Inst <"v_ldexp_f16", VOP_F16_F16_I32, AMDGPUldexp>;
|
|
|
|
let isCommutable = 1 in {
|
|
defm V_ADD_F16 : VOP2Inst <"v_add_f16", VOP_F16_F16_F16, fadd>;
|
|
defm V_SUB_F16 : VOP2Inst <"v_sub_f16", VOP_F16_F16_F16, fsub>;
|
|
defm V_SUBREV_F16 : VOP2Inst <"v_subrev_f16", VOP_F16_F16_F16, null_frag, "v_sub_f16">;
|
|
defm V_MUL_F16 : VOP2Inst <"v_mul_f16", VOP_F16_F16_F16, fmul>;
|
|
def V_MADAK_F16 : VOP2_Pseudo <"v_madak_f16", VOP_MADAK_F16>;
|
|
defm V_ADD_U16 : VOP2Inst <"v_add_u16", VOP_I16_I16_I16>;
|
|
defm V_SUB_U16 : VOP2Inst <"v_sub_u16" , VOP_I16_I16_I16>;
|
|
defm V_SUBREV_U16 : VOP2Inst <"v_subrev_u16", VOP_I16_I16_I16>;
|
|
defm V_MUL_LO_U16 : VOP2Inst <"v_mul_lo_u16", VOP_I16_I16_I16>;
|
|
defm V_MAX_F16 : VOP2Inst <"v_max_f16", VOP_F16_F16_F16, fmaxnum>;
|
|
defm V_MIN_F16 : VOP2Inst <"v_min_f16", VOP_F16_F16_F16, fminnum>;
|
|
defm V_MAX_U16 : VOP2Inst <"v_max_u16", VOP_I16_I16_I16>;
|
|
defm V_MAX_I16 : VOP2Inst <"v_max_i16", VOP_I16_I16_I16>;
|
|
defm V_MIN_U16 : VOP2Inst <"v_min_u16", VOP_I16_I16_I16>;
|
|
defm V_MIN_I16 : VOP2Inst <"v_min_i16", VOP_I16_I16_I16>;
|
|
|
|
let Constraints = "$vdst = $src2", DisableEncoding="$src2",
|
|
isConvertibleToThreeAddress = 1 in {
|
|
defm V_MAC_F16 : VOP2Inst <"v_mac_f16", VOP_MAC_F16>;
|
|
}
|
|
} // End isCommutable = 1
|
|
|
|
} // End SubtargetPredicate = isVI
|
|
|
|
// Note: 16-bit instructions produce a 0 result in the high 16-bits.
|
|
multiclass Arithmetic_i16_Pats <SDPatternOperator op, Instruction inst> {
|
|
|
|
def : Pat<
|
|
(op i16:$src0, i16:$src1),
|
|
(inst $src0, $src1)
|
|
>;
|
|
|
|
def : Pat<
|
|
(i32 (zext (op i16:$src0, i16:$src1))),
|
|
(inst $src0, $src1)
|
|
>;
|
|
|
|
def : Pat<
|
|
(i64 (zext (op i16:$src0, i16:$src1))),
|
|
(REG_SEQUENCE VReg_64,
|
|
(inst $src0, $src1), sub0,
|
|
(V_MOV_B32_e32 (i32 0)), sub1)
|
|
>;
|
|
|
|
}
|
|
|
|
multiclass Bits_OpsRev_i16_Pats <SDPatternOperator op, Instruction inst> {
|
|
|
|
def : Pat<
|
|
(op i16:$src0, i32:$src1),
|
|
(inst $src1, $src0)
|
|
>;
|
|
|
|
def : Pat<
|
|
(i32 (zext (op i16:$src0, i32:$src1))),
|
|
(inst $src1, $src0)
|
|
>;
|
|
|
|
|
|
def : Pat<
|
|
(i64 (zext (op i16:$src0, i32:$src1))),
|
|
(REG_SEQUENCE VReg_64,
|
|
(inst $src1, $src0), sub0,
|
|
(V_MOV_B32_e32 (i32 0)), sub1)
|
|
>;
|
|
}
|
|
|
|
class ZExt_i16_i1_Pat <SDNode ext> : Pat <
|
|
(i16 (ext i1:$src)),
|
|
(V_CNDMASK_B32_e64 (i32 0), (i32 1), $src)
|
|
>;
|
|
|
|
let Predicates = [isVI] in {
|
|
|
|
defm : Arithmetic_i16_Pats<add, V_ADD_U16_e32>;
|
|
defm : Arithmetic_i16_Pats<mul, V_MUL_LO_U16_e32>;
|
|
defm : Arithmetic_i16_Pats<sub, V_SUB_U16_e32>;
|
|
defm : Arithmetic_i16_Pats<smin, V_MIN_I16_e32>;
|
|
defm : Arithmetic_i16_Pats<smax, V_MAX_I16_e32>;
|
|
defm : Arithmetic_i16_Pats<umin, V_MIN_U16_e32>;
|
|
defm : Arithmetic_i16_Pats<umax, V_MAX_U16_e32>;
|
|
|
|
def : Pat <
|
|
(and i16:$src0, i16:$src1),
|
|
(V_AND_B32_e32 $src0, $src1)
|
|
>;
|
|
|
|
def : Pat <
|
|
(or i16:$src0, i16:$src1),
|
|
(V_OR_B32_e32 $src0, $src1)
|
|
>;
|
|
|
|
def : Pat <
|
|
(xor i16:$src0, i16:$src1),
|
|
(V_XOR_B32_e32 $src0, $src1)
|
|
>;
|
|
|
|
defm : Bits_OpsRev_i16_Pats<shl, V_LSHLREV_B16_e32>;
|
|
defm : Bits_OpsRev_i16_Pats<srl, V_LSHRREV_B16_e32>;
|
|
defm : Bits_OpsRev_i16_Pats<sra, V_ASHRREV_B16_e32>;
|
|
|
|
def : ZExt_i16_i1_Pat<zext>;
|
|
def : ZExt_i16_i1_Pat<anyext>;
|
|
|
|
def : Pat <
|
|
(i16 (sext i1:$src)),
|
|
(V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src)
|
|
>;
|
|
|
|
} // End Predicates = [isVI]
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// SI
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
let AssemblerPredicates = [isSICI], DecoderNamespace = "SICI" in {
|
|
|
|
multiclass VOP2_Real_si <bits<6> op> {
|
|
def _si :
|
|
VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>,
|
|
VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
|
|
}
|
|
|
|
multiclass VOP2_Real_MADK_si <bits<6> op> {
|
|
def _si : VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>,
|
|
VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
|
|
}
|
|
|
|
multiclass VOP2_Real_e32_si <bits<6> op> {
|
|
def _e32_si :
|
|
VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>,
|
|
VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
|
|
}
|
|
|
|
multiclass VOP2_Real_e32e64_si <bits<6> op> : VOP2_Real_e32_si<op> {
|
|
def _e64_si :
|
|
VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
|
|
VOP3e_si <{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
|
|
}
|
|
|
|
multiclass VOP2be_Real_e32e64_si <bits<6> op> : VOP2_Real_e32_si<op> {
|
|
def _e64_si :
|
|
VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
|
|
VOP3be_si <{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
|
|
}
|
|
|
|
} // End AssemblerPredicates = [isSICI], DecoderNamespace = "SICI"
|
|
|
|
defm V_CNDMASK_B32 : VOP2_Real_e32e64_si <0x0>;
|
|
defm V_ADD_F32 : VOP2_Real_e32e64_si <0x3>;
|
|
defm V_SUB_F32 : VOP2_Real_e32e64_si <0x4>;
|
|
defm V_SUBREV_F32 : VOP2_Real_e32e64_si <0x5>;
|
|
defm V_MUL_LEGACY_F32 : VOP2_Real_e32e64_si <0x7>;
|
|
defm V_MUL_F32 : VOP2_Real_e32e64_si <0x8>;
|
|
defm V_MUL_I32_I24 : VOP2_Real_e32e64_si <0x9>;
|
|
defm V_MUL_HI_I32_I24 : VOP2_Real_e32e64_si <0xa>;
|
|
defm V_MUL_U32_U24 : VOP2_Real_e32e64_si <0xb>;
|
|
defm V_MUL_HI_U32_U24 : VOP2_Real_e32e64_si <0xc>;
|
|
defm V_MIN_F32 : VOP2_Real_e32e64_si <0xf>;
|
|
defm V_MAX_F32 : VOP2_Real_e32e64_si <0x10>;
|
|
defm V_MIN_I32 : VOP2_Real_e32e64_si <0x11>;
|
|
defm V_MAX_I32 : VOP2_Real_e32e64_si <0x12>;
|
|
defm V_MIN_U32 : VOP2_Real_e32e64_si <0x13>;
|
|
defm V_MAX_U32 : VOP2_Real_e32e64_si <0x14>;
|
|
defm V_LSHRREV_B32 : VOP2_Real_e32e64_si <0x16>;
|
|
defm V_ASHRREV_I32 : VOP2_Real_e32e64_si <0x18>;
|
|
defm V_LSHLREV_B32 : VOP2_Real_e32e64_si <0x1a>;
|
|
defm V_AND_B32 : VOP2_Real_e32e64_si <0x1b>;
|
|
defm V_OR_B32 : VOP2_Real_e32e64_si <0x1c>;
|
|
defm V_XOR_B32 : VOP2_Real_e32e64_si <0x1d>;
|
|
defm V_MAC_F32 : VOP2_Real_e32e64_si <0x1f>;
|
|
defm V_MADMK_F32 : VOP2_Real_MADK_si <0x20>;
|
|
defm V_MADAK_F32 : VOP2_Real_MADK_si <0x21>;
|
|
defm V_ADD_I32 : VOP2be_Real_e32e64_si <0x25>;
|
|
defm V_SUB_I32 : VOP2be_Real_e32e64_si <0x26>;
|
|
defm V_SUBREV_I32 : VOP2be_Real_e32e64_si <0x27>;
|
|
defm V_ADDC_U32 : VOP2be_Real_e32e64_si <0x28>;
|
|
defm V_SUBB_U32 : VOP2be_Real_e32e64_si <0x29>;
|
|
defm V_SUBBREV_U32 : VOP2be_Real_e32e64_si <0x2a>;
|
|
|
|
defm V_READLANE_B32 : VOP2_Real_si <0x01>;
|
|
defm V_WRITELANE_B32 : VOP2_Real_si <0x02>;
|
|
|
|
defm V_MAC_LEGACY_F32 : VOP2_Real_e32e64_si <0x6>;
|
|
defm V_MIN_LEGACY_F32 : VOP2_Real_e32e64_si <0xd>;
|
|
defm V_MAX_LEGACY_F32 : VOP2_Real_e32e64_si <0xe>;
|
|
defm V_LSHR_B32 : VOP2_Real_e32e64_si <0x15>;
|
|
defm V_ASHR_I32 : VOP2_Real_e32e64_si <0x17>;
|
|
defm V_LSHL_B32 : VOP2_Real_e32e64_si <0x19>;
|
|
|
|
defm V_BFM_B32 : VOP2_Real_e32e64_si <0x1e>;
|
|
defm V_BCNT_U32_B32 : VOP2_Real_e32e64_si <0x22>;
|
|
defm V_MBCNT_LO_U32_B32 : VOP2_Real_e32e64_si <0x23>;
|
|
defm V_MBCNT_HI_U32_B32 : VOP2_Real_e32e64_si <0x24>;
|
|
defm V_LDEXP_F32 : VOP2_Real_e32e64_si <0x2b>;
|
|
defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_e32e64_si <0x2c>;
|
|
defm V_CVT_PKNORM_I16_F32 : VOP2_Real_e32e64_si <0x2d>;
|
|
defm V_CVT_PKNORM_U16_F32 : VOP2_Real_e32e64_si <0x2e>;
|
|
defm V_CVT_PKRTZ_F16_F32 : VOP2_Real_e32e64_si <0x2f>;
|
|
defm V_CVT_PK_U16_U32 : VOP2_Real_e32e64_si <0x30>;
|
|
defm V_CVT_PK_I16_I32 : VOP2_Real_e32e64_si <0x31>;
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// VI
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
class VOP2_SDWA <bits<6> op, VOP2_Pseudo ps, VOPProfile P = ps.Pfl> :
|
|
VOP_SDWA <ps.OpName, P> {
|
|
let Defs = ps.Defs;
|
|
let Uses = ps.Uses;
|
|
let SchedRW = ps.SchedRW;
|
|
let hasSideEffects = ps.hasSideEffects;
|
|
let AsmMatchConverter = "cvtSdwaVOP2";
|
|
|
|
bits<8> vdst;
|
|
bits<8> src1;
|
|
let Inst{8-0} = 0xf9; // sdwa
|
|
let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0);
|
|
let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
|
|
let Inst{30-25} = op;
|
|
let Inst{31} = 0x0; // encoding
|
|
}
|
|
|
|
class VOP2_DPP <bits<6> op, VOP2_Pseudo ps, VOPProfile P = ps.Pfl> :
|
|
VOP_DPP <ps.OpName, P> {
|
|
let Defs = ps.Defs;
|
|
let Uses = ps.Uses;
|
|
let SchedRW = ps.SchedRW;
|
|
let hasSideEffects = ps.hasSideEffects;
|
|
|
|
bits<8> vdst;
|
|
bits<8> src1;
|
|
let Inst{8-0} = 0xfa; //dpp
|
|
let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0);
|
|
let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
|
|
let Inst{30-25} = op;
|
|
let Inst{31} = 0x0; //encoding
|
|
}
|
|
|
|
let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in {
|
|
|
|
multiclass VOP32_Real_vi <bits<10> op> {
|
|
def _vi :
|
|
VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.VI>,
|
|
VOP3e_vi<op, !cast<VOP2_Pseudo>(NAME).Pfl>;
|
|
}
|
|
|
|
multiclass VOP2_Real_MADK_vi <bits<6> op> {
|
|
def _vi : VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.VI>,
|
|
VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
|
|
}
|
|
|
|
multiclass VOP2_Real_e32_vi <bits<6> op> {
|
|
def _e32_vi :
|
|
VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>,
|
|
VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
|
|
}
|
|
|
|
multiclass VOP2_Real_e64_vi <bits<10> op> {
|
|
def _e64_vi :
|
|
VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
|
|
VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
|
|
}
|
|
|
|
multiclass VOP2be_Real_e32e64_vi <bits<6> op> : VOP2_Real_e32_vi<op> {
|
|
def _e64_vi :
|
|
VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
|
|
VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
|
|
}
|
|
|
|
multiclass Base_VOP2_Real_e32e64_vi <bits<6> op> :
|
|
VOP2_Real_e32_vi<op>,
|
|
VOP2_Real_e64_vi<{0, 1, 0, 0, op{5-0}}>;
|
|
|
|
} // End AssemblerPredicates = [isVI], DecoderNamespace = "VI"
|
|
|
|
multiclass VOP2_Real_e32e64_vi <bits<6> op> :
|
|
Base_VOP2_Real_e32e64_vi<op> {
|
|
// for now left sdwa/dpp only for asm/dasm
|
|
// TODO: add corresponding pseudo
|
|
def _sdwa : VOP2_SDWA<op, !cast<VOP2_Pseudo>(NAME#"_e32")>;
|
|
def _dpp : VOP2_DPP<op, !cast<VOP2_Pseudo>(NAME#"_e32")>;
|
|
}
|
|
|
|
defm V_CNDMASK_B32 : Base_VOP2_Real_e32e64_vi <0x0>;
|
|
defm V_ADD_F32 : VOP2_Real_e32e64_vi <0x1>;
|
|
defm V_SUB_F32 : VOP2_Real_e32e64_vi <0x2>;
|
|
defm V_SUBREV_F32 : VOP2_Real_e32e64_vi <0x3>;
|
|
defm V_MUL_LEGACY_F32 : VOP2_Real_e32e64_vi <0x4>;
|
|
defm V_MUL_F32 : VOP2_Real_e32e64_vi <0x5>;
|
|
defm V_MUL_I32_I24 : VOP2_Real_e32e64_vi <0x6>;
|
|
defm V_MUL_HI_I32_I24 : VOP2_Real_e32e64_vi <0x7>;
|
|
defm V_MUL_U32_U24 : VOP2_Real_e32e64_vi <0x8>;
|
|
defm V_MUL_HI_U32_U24 : VOP2_Real_e32e64_vi <0x9>;
|
|
defm V_MIN_F32 : VOP2_Real_e32e64_vi <0xa>;
|
|
defm V_MAX_F32 : VOP2_Real_e32e64_vi <0xb>;
|
|
defm V_MIN_I32 : VOP2_Real_e32e64_vi <0xc>;
|
|
defm V_MAX_I32 : VOP2_Real_e32e64_vi <0xd>;
|
|
defm V_MIN_U32 : VOP2_Real_e32e64_vi <0xe>;
|
|
defm V_MAX_U32 : VOP2_Real_e32e64_vi <0xf>;
|
|
defm V_LSHRREV_B32 : VOP2_Real_e32e64_vi <0x10>;
|
|
defm V_ASHRREV_I32 : VOP2_Real_e32e64_vi <0x11>;
|
|
defm V_LSHLREV_B32 : VOP2_Real_e32e64_vi <0x12>;
|
|
defm V_AND_B32 : VOP2_Real_e32e64_vi <0x13>;
|
|
defm V_OR_B32 : VOP2_Real_e32e64_vi <0x14>;
|
|
defm V_XOR_B32 : VOP2_Real_e32e64_vi <0x15>;
|
|
defm V_MAC_F32 : VOP2_Real_e32e64_vi <0x16>;
|
|
defm V_MADMK_F32 : VOP2_Real_MADK_vi <0x17>;
|
|
defm V_MADAK_F32 : VOP2_Real_MADK_vi <0x18>;
|
|
defm V_ADD_I32 : VOP2be_Real_e32e64_vi <0x19>;
|
|
defm V_SUB_I32 : VOP2be_Real_e32e64_vi <0x1a>;
|
|
defm V_SUBREV_I32 : VOP2be_Real_e32e64_vi <0x1b>;
|
|
defm V_ADDC_U32 : VOP2be_Real_e32e64_vi <0x1c>;
|
|
defm V_SUBB_U32 : VOP2be_Real_e32e64_vi <0x1d>;
|
|
defm V_SUBBREV_U32 : VOP2be_Real_e32e64_vi <0x1e>;
|
|
|
|
defm V_READLANE_B32 : VOP32_Real_vi <0x289>;
|
|
defm V_WRITELANE_B32 : VOP32_Real_vi <0x28a>;
|
|
|
|
defm V_BFM_B32 : VOP2_Real_e64_vi <0x293>;
|
|
defm V_BCNT_U32_B32 : VOP2_Real_e64_vi <0x28b>;
|
|
defm V_MBCNT_LO_U32_B32 : VOP2_Real_e64_vi <0x28c>;
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defm V_MBCNT_HI_U32_B32 : VOP2_Real_e64_vi <0x28d>;
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defm V_LDEXP_F32 : VOP2_Real_e64_vi <0x288>;
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defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_e64_vi <0x1f0>;
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defm V_CVT_PKNORM_I16_F32 : VOP2_Real_e64_vi <0x294>;
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defm V_CVT_PKNORM_U16_F32 : VOP2_Real_e64_vi <0x295>;
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defm V_CVT_PKRTZ_F16_F32 : VOP2_Real_e64_vi <0x296>;
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defm V_CVT_PK_U16_U32 : VOP2_Real_e64_vi <0x297>;
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defm V_CVT_PK_I16_I32 : VOP2_Real_e64_vi <0x298>;
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defm V_ADD_F16 : VOP2_Real_e32e64_vi <0x1f>;
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defm V_SUB_F16 : VOP2_Real_e32e64_vi <0x20>;
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defm V_SUBREV_F16 : VOP2_Real_e32e64_vi <0x21>;
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defm V_MUL_F16 : VOP2_Real_e32e64_vi <0x22>;
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defm V_MAC_F16 : VOP2_Real_e32e64_vi <0x23>;
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defm V_MADMK_F16 : VOP2_Real_MADK_vi <0x24>;
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defm V_MADAK_F16 : VOP2_Real_MADK_vi <0x25>;
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defm V_ADD_U16 : VOP2_Real_e32e64_vi <0x26>;
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defm V_SUB_U16 : VOP2_Real_e32e64_vi <0x27>;
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defm V_SUBREV_U16 : VOP2_Real_e32e64_vi <0x28>;
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defm V_MUL_LO_U16 : VOP2_Real_e32e64_vi <0x29>;
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defm V_LSHLREV_B16 : VOP2_Real_e32e64_vi <0x2a>;
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defm V_LSHRREV_B16 : VOP2_Real_e32e64_vi <0x2b>;
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defm V_ASHRREV_B16 : VOP2_Real_e32e64_vi <0x2c>;
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defm V_MAX_F16 : VOP2_Real_e32e64_vi <0x2d>;
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defm V_MIN_F16 : VOP2_Real_e32e64_vi <0x2e>;
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defm V_MAX_U16 : VOP2_Real_e32e64_vi <0x2f>;
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defm V_MAX_I16 : VOP2_Real_e32e64_vi <0x30>;
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defm V_MIN_U16 : VOP2_Real_e32e64_vi <0x31>;
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defm V_MIN_I16 : VOP2_Real_e32e64_vi <0x32>;
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defm V_LDEXP_F16 : VOP2_Real_e32e64_vi <0x33>;
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let SubtargetPredicate = isVI in {
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// Aliases to simplify matching of floating-point instructions that
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// are VOP2 on SI and VOP3 on VI.
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class SI2_VI3Alias <string name, Instruction inst> : InstAlias <
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name#" $dst, $src0, $src1",
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(inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0, 0)
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>, PredicateControl {
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let UseInstAsmMatchConverter = 0;
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let AsmVariantName = AMDGPUAsmVariants.VOP3;
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}
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def : SI2_VI3Alias <"v_ldexp_f32", V_LDEXP_F32_e64_vi>;
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def : SI2_VI3Alias <"v_cvt_pkaccum_u8_f32", V_CVT_PKACCUM_U8_F32_e64_vi>;
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def : SI2_VI3Alias <"v_cvt_pknorm_i16_f32", V_CVT_PKNORM_I16_F32_e64_vi>;
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def : SI2_VI3Alias <"v_cvt_pknorm_u16_f32", V_CVT_PKNORM_U16_F32_e64_vi>;
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def : SI2_VI3Alias <"v_cvt_pkrtz_f16_f32", V_CVT_PKRTZ_F16_F32_e64_vi>;
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} // End SubtargetPredicate = isVI
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