llvm-project/llvm/lib/Target/AMDGPU
Matt Arsenault d4da0edd98 AMDGPU: Implement isCheapAddrSpaceCast
llvm-svn: 288523
2016-12-02 18:12:53 +00:00
..
AsmParser AMDGPU: Fix return after else 2016-11-15 19:58:54 +00:00
Disassembler AMDGPU: Disallow exec as SMEM instruction operand 2016-11-29 19:39:53 +00:00
InstPrinter AMDGPU: Fix formatting of 1/2pi immediate 2016-11-15 00:04:33 +00:00
MCTargetDesc Check that emitted instructions meet their predicates on all targets except ARM, Mips, and X86. 2016-11-19 13:05:44 +00:00
TargetInfo Move the global variables representing each Target behind accessor function 2016-10-09 23:00:34 +00:00
Utils AMDGPU/SI: Handle hazard with > 8 byte VMEM stores 2016-10-27 23:05:31 +00:00
AMDGPU.h Move the global variables representing each Target behind accessor function 2016-10-09 23:00:34 +00:00
AMDGPU.td [AMDGPU] Add f16 support (VI+) 2016-11-13 07:01:11 +00:00
AMDGPUAlwaysInlinePass.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
AMDGPUAnnotateKernelFeatures.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
AMDGPUAnnotateUniformValues.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
AMDGPUAsmPrinter.cpp AMDGPU: Emit runtime metadata as a note element in .note section 2016-11-10 21:18:49 +00:00
AMDGPUAsmPrinter.h AMDGPU: Emit runtime metadata as a note element in .note section 2016-11-10 21:18:49 +00:00
AMDGPUCallLowering.cpp GlobalISel: pass Function to lowerFormalArguments directly (NFC). 2016-09-21 12:57:35 +00:00
AMDGPUCallLowering.h GlobalISel: pass Function to lowerFormalArguments directly (NFC). 2016-09-21 12:57:35 +00:00
AMDGPUCallingConv.td AMDGPU: Fix kernel argument alignment impacting stack size 2016-06-18 05:15:53 +00:00
AMDGPUCodeGenPrepare.cpp [AMDGPU] AMDGPUCodeGenPrepare: remove extra ';' 2016-10-07 14:39:53 +00:00
AMDGPUFrameLowering.cpp MachineFunction: Return reference for getFrameInfo(); NFC 2016-07-28 18:40:00 +00:00
AMDGPUFrameLowering.h AMDGPU: Move R600 only pieces into R600 classes 2016-07-09 18:11:15 +00:00
AMDGPUISelDAGToDAG.cpp AMDGPU/SI: Add back reverted SGPR spilling code, but disable it 2016-11-25 17:37:09 +00:00
AMDGPUISelLowering.cpp [AMDGPU] Allow hoisting of comparisons out of a loop and eliminate condition copies 2016-11-28 18:58:49 +00:00
AMDGPUISelLowering.h [DAG Combiner] Fix the native computation of the Newton series for reciprocals 2016-11-10 23:31:06 +00:00
AMDGPUInstrInfo.cpp MachineScheduler: Export function to construct "default" scheduler. 2016-11-28 20:11:54 +00:00
AMDGPUInstrInfo.h MachineScheduler: Export function to construct "default" scheduler. 2016-11-28 20:11:54 +00:00
AMDGPUInstrInfo.td AMDGPU: Select mulhi 24-bit instructions 2016-08-27 01:32:27 +00:00
AMDGPUInstructions.td [AMDGPU] Add f16 support (VI+) 2016-11-13 07:01:11 +00:00
AMDGPUIntrinsicInfo.cpp AMDGPU: Change fdiv lowering based on !fpmath metadata 2016-07-19 23:16:53 +00:00
AMDGPUIntrinsicInfo.h AMDGPU: Change fdiv lowering based on !fpmath metadata 2016-07-19 23:16:53 +00:00
AMDGPUIntrinsics.td AMDGPU: Remove read_workdim intrinsic 2016-07-25 20:17:02 +00:00
AMDGPUMCInstLower.cpp [AMDGPU] Add wave barrier builtin 2016-11-15 19:00:15 +00:00
AMDGPUMCInstLower.h Reapply "AMDGPU: Support using tablegened MC pseudo expansions" 2016-10-06 17:19:11 +00:00
AMDGPUMachineFunction.cpp AMDGPU: Make AMDGPUMachineFunction fields private 2016-07-26 16:45:58 +00:00
AMDGPUMachineFunction.h AMDGPU: Make AMDGPUMachineFunction fields private 2016-07-26 16:45:58 +00:00
AMDGPUOpenCLImageTypeLoweringPass.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
AMDGPUPTNote.h AMDGPU: Emit runtime metadata as a note element in .note section 2016-11-10 21:18:49 +00:00
AMDGPUPromoteAlloca.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
AMDGPURegisterInfo.cpp AMDGPU: Move R600 only pieces into R600 classes 2016-07-09 18:11:15 +00:00
AMDGPURegisterInfo.h AMDGPU: Move R600 only pieces into R600 classes 2016-07-09 18:11:15 +00:00
AMDGPURegisterInfo.td
AMDGPURuntimeMetadata.h AMDGPU: Attempt to fix build failure on x86-64 selfhost build 2016-11-11 02:48:50 +00:00
AMDGPUSubtarget.cpp [AMDGPU] Add f16 support (VI+) 2016-11-13 07:01:11 +00:00
AMDGPUSubtarget.h [AMDGPU] Add f16 support (VI+) 2016-11-13 07:01:11 +00:00
AMDGPUTargetMachine.cpp MachineScheduler: Export function to construct "default" scheduler. 2016-11-28 20:11:54 +00:00
AMDGPUTargetMachine.h AMDGPU: Delete more dead code 2016-07-22 17:01:25 +00:00
AMDGPUTargetObjectFile.cpp Target: Change various section classifiers in TargetLoweringObjectFile to take a GlobalObject. 2016-10-24 19:23:39 +00:00
AMDGPUTargetObjectFile.h Target: Change various section classifiers in TargetLoweringObjectFile to take a GlobalObject. 2016-10-24 19:23:39 +00:00
AMDGPUTargetTransformInfo.cpp Add new target hooks for LoadStoreVectorizer 2016-10-03 10:31:34 +00:00
AMDGPUTargetTransformInfo.h Do a sweep over move ctors and remove those that are identical to the default. 2016-10-20 12:20:28 +00:00
AMDILCFGStructurizer.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
AMDKernelCodeT.h [AMDGPU] fix amd_kernel_code_t bit field position as per spec (added missing reserved fields) 2016-02-24 10:54:25 +00:00
BUFInstructions.td AMDGPU: Add VI i16 support 2016-11-10 16:02:37 +00:00
CIInstructions.td [AMDGPU] Refactor VOP1 and VOP2 instruction TD definitions 2016-09-23 09:08:07 +00:00
CMakeLists.txt Reapply "AMDGPU: Support using tablegened MC pseudo expansions" 2016-10-06 17:19:11 +00:00
CaymanInstructions.td AMDGPU: Select mulhi 24-bit instructions 2016-08-27 01:32:27 +00:00
DSInstructions.td AMDGPU: Add VI i16 support 2016-11-10 16:02:37 +00:00
EvergreenInstructions.td AMDGPU: Select mulhi 24-bit instructions 2016-08-27 01:32:27 +00:00
FLATInstructions.td AMDGPU: Rename flat operands to match mubuf 2016-11-29 19:30:44 +00:00
GCNHazardRecognizer.cpp AMDGPU: Rename flat operands to match mubuf 2016-11-29 19:30:44 +00:00
GCNHazardRecognizer.h AMDGPU/SI: Handle hazard with s_rfe_b64 2016-10-27 23:50:21 +00:00
GCNSchedStrategy.cpp AMDGPU: Whitespace fixes 2016-11-01 00:55:14 +00:00
GCNSchedStrategy.h AMDGPU/SI: Implement a custom MachineSchedStrategy 2016-08-29 19:42:52 +00:00
LLVMBuild.txt AMDGPU: Prune AMDGPUAsmParser in libdeps. 2016-07-09 07:54:27 +00:00
MIMGInstructions.td [AMDGPU] TableGen: change individual instruction flags to bit type from bits<1> 2016-11-15 13:39:07 +00:00
Processors.td AMDGPU: Refactor processor definition to use ISA version features 2016-10-26 16:37:56 +00:00
R600ClauseMergePass.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
R600ControlFlowFinalizer.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
R600Defines.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
R600EmitClauseMarkers.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
R600ExpandSpecialInstrs.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
R600FrameLowering.cpp AMDGPU: Cleanup subtarget handling. 2016-06-24 06:30:11 +00:00
R600FrameLowering.h AMDGPU: Cleanup subtarget handling. 2016-06-24 06:30:11 +00:00
R600ISelLowering.cpp AMDGPU: Refactor kernel argument lowering 2016-09-16 21:53:00 +00:00
R600ISelLowering.h AMDGPU: Fix i1 fp_to_int 2016-07-22 17:01:21 +00:00
R600InstrFormats.td AMDGPU/R600: Convert buffer id to VTX_READ input 2016-08-15 21:38:30 +00:00
R600InstrInfo.cpp Finish renaming remaining analyzeBranch functions 2016-09-14 20:43:16 +00:00
R600InstrInfo.h Finish renaming remaining analyzeBranch functions 2016-09-14 20:43:16 +00:00
R600Instructions.td Target: Remove unused patterns and transforms. NFC. 2016-10-07 00:30:49 +00:00
R600Intrinsics.td AMDGPU: Fix TargetPrefix for remaining r600 intrinsics 2016-07-15 21:27:08 +00:00
R600MachineFunctionInfo.cpp AMDGPU: Delete more dead code 2016-07-22 17:01:25 +00:00
R600MachineFunctionInfo.h AMDGPU: Delete more dead code 2016-07-22 17:01:25 +00:00
R600MachineScheduler.cpp CodeGen: Use MachineInstr& in TargetInstrInfo, NFC 2016-06-30 00:01:54 +00:00
R600MachineScheduler.h AMDGPU: Cleanup subtarget handling. 2016-06-24 06:30:11 +00:00
R600OptimizeVectorRegisters.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
R600Packetizer.cpp Fix spelling mistakes in AMDGPU target comments. NFC. 2016-11-18 11:04:02 +00:00
R600RegisterInfo.cpp AMDGPU: Move R600 only pieces into R600 classes 2016-07-09 18:11:15 +00:00
R600RegisterInfo.h AMDGPU: Move R600 only pieces into R600 classes 2016-07-09 18:11:15 +00:00
R600RegisterInfo.td
R600Schedule.td AMDGPU: Fix trailing whitespace 2016-06-10 02:18:02 +00:00
R700Instructions.td
SIAnnotateControlFlow.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
SIDebuggerInsertNops.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
SIDefines.h AMDGPU: Workaround for instruction size with literals 2016-11-01 20:42:24 +00:00
SIFixControlFlowLiveIntervals.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
SIFixSGPRCopies.cpp AMDGPU/SI: Avoid moving PHIs to VALU when phi values are defined in scalar branches 2016-11-29 00:46:46 +00:00
SIFoldOperands.cpp AMDGPU: Refactor immediate folding logic 2016-11-29 19:20:42 +00:00
SIFrameLowering.cpp AMDGPU: Fix using incorrect private resource with no allocation 2016-10-28 19:43:31 +00:00
SIFrameLowering.h AMDGPU: Refactor frame lowering 2016-08-31 21:52:21 +00:00
SIISelLowering.cpp AMDGPU: Implement isCheapAddrSpaceCast 2016-12-02 18:12:53 +00:00
SIISelLowering.h AMDGPU: Implement isCheapAddrSpaceCast 2016-12-02 18:12:53 +00:00
SIInsertSkips.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
SIInsertWaits.cpp AMDGPU: Rename flat operands to match mubuf 2016-11-29 19:30:44 +00:00
SIInstrFormats.td [AMDGPU] TableGen: change individual instruction flags to bit type from bits<1> 2016-11-15 13:39:07 +00:00
SIInstrInfo.cpp AMDGPU: Rename flat operands to match mubuf 2016-11-29 19:30:44 +00:00
SIInstrInfo.h AMDGPU/SI: Avoid creating unnecessary copies in the SIFixSGPRCopies pass 2016-11-16 18:42:17 +00:00
SIInstrInfo.td [AMDGPU] Change frexp.exp intrinsic to return i16 for f16 input 2016-11-18 22:31:08 +00:00
SIInstructions.td AMDGPU/SI: Use float as the operand type for amdgcn.interp intrinsics 2016-11-26 02:26:04 +00:00
SIIntrinsics.td AMDGPU: Allow some control flow intrinsics to be CSEd 2016-09-16 22:11:18 +00:00
SILoadStoreOptimizer.cpp [AMDGPU][CodeGen] To improve CGEMM performance: combine LDS reads. 2016-11-03 14:37:13 +00:00
SILowerControlFlow.cpp [AMDGPU] Allow hoisting of comparisons out of a loop and eliminate condition copies 2016-11-28 18:58:49 +00:00
SILowerI1Copies.cpp [AMDGPU] Allow hoisting of comparisons out of a loop and eliminate condition copies 2016-11-28 18:58:49 +00:00
SIMachineFunctionInfo.cpp AMDGPU/SI: Add support for triples with the mesa3d operating system 2016-09-16 21:34:26 +00:00
SIMachineFunctionInfo.h [AMDGPU] Wave and register controls 2016-09-06 20:22:28 +00:00
SIMachineScheduler.cpp Fix spelling mistakes in AMDGPU target comments. NFC. 2016-11-18 11:04:02 +00:00
SIMachineScheduler.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
SIOptimizeExecMasking.cpp AMDGPU: Fix use-after-free in SIOptimizeExecMasking 2016-10-07 08:40:14 +00:00
SIRegisterInfo.cpp AMDGPU: Use wider scalar spills for SGPR spilling 2016-12-02 00:54:45 +00:00
SIRegisterInfo.h AMDGPU/SI: Add back reverted SGPR spilling code, but disable it 2016-11-25 17:37:09 +00:00
SIRegisterInfo.td AMDGPU: Disallow exec as SMEM instruction operand 2016-11-29 19:39:53 +00:00
SISchedule.td AMDGPU/SI: Implement a custom MachineSchedStrategy 2016-08-29 19:42:52 +00:00
SIShrinkInstructions.cpp [AMDGPU] Add f16 support (VI+) 2016-11-13 07:01:11 +00:00
SITypeRewriter.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
SIWholeQuadMode.cpp AMDGPU/SI: Add back reverted SGPR spilling code, but disable it 2016-11-25 17:37:09 +00:00
SMInstructions.td AMDGPU: Disallow exec as SMEM instruction operand 2016-11-29 19:39:53 +00:00
SOPInstructions.td AMDGPU: Add VI i16 support 2016-11-10 16:02:37 +00:00
VIInstrFormats.td [AMDGPU] Refactor VOP1 and VOP2 instruction TD definitions 2016-09-23 09:08:07 +00:00
VIInstructions.td AMDGPU: Add VI i16 support 2016-11-10 16:02:37 +00:00
VOP1Instructions.td Check that emitted instructions meet their predicates on all targets except ARM, Mips, and X86. 2016-11-19 13:05:44 +00:00
VOP2Instructions.td AMDGPU/SI: Remove zero_extend patterns for i16 ops selected to 32-bit insts 2016-11-18 13:53:34 +00:00
VOP3Instructions.td [AMDGPU] Handle f16 select{_cc} 2016-11-16 03:16:26 +00:00
VOPCInstructions.td [AMDGPU] Add f16 support (VI+) 2016-11-13 07:01:11 +00:00
VOPInstructions.td Fix spelling mistakes in AMDGPU target comments. NFC. 2016-11-18 11:04:02 +00:00