forked from OSchip/llvm-project
38 lines
1.2 KiB
CMake
38 lines
1.2 KiB
CMake
set(LLVM_TARGET_DEFINITIONS RISCV.td)
|
|
|
|
tablegen(LLVM RISCVGenAsmMatcher.inc -gen-asm-matcher)
|
|
tablegen(LLVM RISCVGenAsmWriter.inc -gen-asm-writer)
|
|
tablegen(LLVM RISCVGenCompressInstEmitter.inc -gen-compress-inst-emitter)
|
|
tablegen(LLVM RISCVGenDAGISel.inc -gen-dag-isel)
|
|
tablegen(LLVM RISCVGenDisassemblerTables.inc -gen-disassembler)
|
|
tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
|
|
tablegen(LLVM RISCVGenMCCodeEmitter.inc -gen-emitter)
|
|
tablegen(LLVM RISCVGenMCPseudoLowering.inc -gen-pseudo-lowering)
|
|
tablegen(LLVM RISCVGenRegisterInfo.inc -gen-register-info)
|
|
tablegen(LLVM RISCVGenSubtargetInfo.inc -gen-subtarget)
|
|
tablegen(LLVM RISCVGenSystemOperands.inc -gen-searchable-tables)
|
|
|
|
add_public_tablegen_target(RISCVCommonTableGen)
|
|
|
|
add_llvm_target(RISCVCodeGen
|
|
RISCVAsmPrinter.cpp
|
|
RISCVExpandPseudoInsts.cpp
|
|
RISCVFrameLowering.cpp
|
|
RISCVInstrInfo.cpp
|
|
RISCVISelDAGToDAG.cpp
|
|
RISCVISelLowering.cpp
|
|
RISCVMCInstLower.cpp
|
|
RISCVMergeBaseOffset.cpp
|
|
RISCVRegisterInfo.cpp
|
|
RISCVSubtarget.cpp
|
|
RISCVTargetMachine.cpp
|
|
RISCVTargetObjectFile.cpp
|
|
RISCVTargetTransformInfo.cpp
|
|
)
|
|
|
|
add_subdirectory(AsmParser)
|
|
add_subdirectory(Disassembler)
|
|
add_subdirectory(MCTargetDesc)
|
|
add_subdirectory(TargetInfo)
|
|
add_subdirectory(Utils)
|