| .. |
|
AsmParser
|
AMDGPU: Remove max_scratch_backing_memory_byte_size from kernel header
|
2018-04-09 20:47:22 +00:00 |
|
Disassembler
|
AMDGPU/MC: Allow disassembling without symbol info
|
2018-04-10 15:46:43 +00:00 |
|
InstPrinter
|
[AMDGPU][MC][GFX8][GFX9][DISASSEMBLER] Added "_e32" suffix to 32-bit VINTRP opcodes
|
2018-03-16 16:38:04 +00:00 |
|
MCTargetDesc
|
AMDGPU/Metadata: Always report a fixed number of hidden arguments
|
2018-04-05 20:46:04 +00:00 |
|
TargetInfo
|
Add backend name to Target to enable runtime info to be fed back into TableGen
|
2017-11-15 23:55:44 +00:00 |
|
Utils
|
[AMDGPU] Enabled v2.16 literals for VOP3P
|
2018-04-17 23:09:05 +00:00 |
|
AMDGPU.h
|
[AMDGPU] Change constant addr space to 4
|
2018-02-13 18:00:25 +00:00 |
|
AMDGPU.td
|
AMDGPU: enable 128-bit for local addr space under an option
|
2018-04-10 22:48:23 +00:00 |
|
AMDGPUAliasAnalysis.cpp
|
[AMDGPU] Change constant addr space to 4
|
2018-02-13 18:00:25 +00:00 |
|
AMDGPUAliasAnalysis.h
|
[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
|
2017-08-08 23:53:55 +00:00 |
|
AMDGPUAlwaysInlinePass.cpp
|
AMDGPU: Add option to stress calls
|
2017-09-21 07:00:48 +00:00 |
|
AMDGPUAnnotateKernelFeatures.cpp
|
[Analysis] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes. Also affected in files (NFC).
|
2017-08-31 21:56:16 +00:00 |
|
AMDGPUAnnotateUniformValues.cpp
|
AMDGPU: Fix converting unanalyzable global loads to SMRD
|
2017-07-12 23:06:18 +00:00 |
|
AMDGPUArgumentUsageInfo.cpp
|
[CodeGen] Rename functions PrintReg* to printReg*
|
2017-11-28 12:42:37 +00:00 |
|
AMDGPUArgumentUsageInfo.h
|
[AMDGPU] Fixed MSVC build break
|
2017-08-04 10:53:07 +00:00 |
|
AMDGPUAsmPrinter.cpp
|
[AMDGPU] Ensure there are enough registers for wave dispatch
|
2018-04-11 17:18:36 +00:00 |
|
AMDGPUAsmPrinter.h
|
[AMDGPU] add labels to +DumpCode output
|
2017-12-08 14:09:34 +00:00 |
|
AMDGPUCallLowering.cpp
|
[AMDGPU] Change constant addr space to 4
|
2018-02-13 18:00:25 +00:00 |
|
AMDGPUCallLowering.h
|
AMDGPU: Start defining a calling convention
|
2017-05-17 21:56:25 +00:00 |
|
AMDGPUCallingConv.td
|
AMDGPU: Initial implementation of calls
|
2017-08-01 19:54:18 +00:00 |
|
AMDGPUCodeGenPrepare.cpp
|
Reapply "AMDGPU: Add 32-bit constant address space"
|
2018-02-09 16:57:57 +00:00 |
|
AMDGPUFrameLowering.cpp
|
…
|
|
|
AMDGPUFrameLowering.h
|
Move TargetFrameLowering.h to CodeGen where it's implemented
|
2017-11-03 22:32:11 +00:00 |
|
AMDGPUGenRegisterBankInfo.def
|
AMDGPU/GlobalISel: Use a more correct getValueMapping
|
2018-03-01 21:08:51 +00:00 |
|
AMDGPUISelDAGToDAG.cpp
|
[IR][CodeGen] Remove dependency on EVT from IR/Function.cpp. Move EVT to CodeGen layer.
|
2018-03-29 17:21:10 +00:00 |
|
AMDGPUISelLowering.cpp
|
[AMDGPU] Fix issues for backend divergence tracking
|
2018-04-18 13:53:31 +00:00 |
|
AMDGPUISelLowering.h
|
AMDGPU: Fix build warning about override
|
2018-03-05 16:25:10 +00:00 |
|
AMDGPUInline.cpp
|
[AMDGPU] Port of HSAIL inliner
|
2017-09-20 04:25:58 +00:00 |
|
AMDGPUInstrInfo.cpp
|
AMDGPU: Dimension-aware image intrinsics
|
2018-04-04 10:58:54 +00:00 |
|
AMDGPUInstrInfo.h
|
AMDGPU: Dimension-aware image intrinsics
|
2018-04-04 10:58:54 +00:00 |
|
AMDGPUInstrInfo.td
|
AMDGPU: Add intrinsics llvm.amdgcn.cvt.{pknorm.i16, pknorm.u16, pk.i16, pk.u16}
|
2018-01-31 20:18:04 +00:00 |
|
AMDGPUInstructionSelector.cpp
|
Reapply "AMDGPU: Add 32-bit constant address space"
|
2018-02-09 16:57:57 +00:00 |
|
AMDGPUInstructionSelector.h
|
[globalisel][tablegen] Generate rule coverage and use it to identify untested rules
|
2017-11-16 00:46:35 +00:00 |
|
AMDGPUInstructions.td
|
[AMDGPU] Supported ds_write_b128 generation.
|
2018-03-16 18:12:00 +00:00 |
|
AMDGPUIntrinsicInfo.cpp
|
…
|
|
|
AMDGPUIntrinsicInfo.h
|
…
|
|
|
AMDGPUIntrinsics.td
|
…
|
|
|
AMDGPULegalizerInfo.cpp
|
[IR][CodeGen] Remove dependency on EVT from IR/Function.cpp. Move EVT to CodeGen layer.
|
2018-03-29 17:21:10 +00:00 |
|
AMDGPULegalizerInfo.h
|
AMDGPU/GlobalISel: Pass subtarget + TM to LegalizerInfo
|
2018-03-08 16:24:16 +00:00 |
|
AMDGPULibCalls.cpp
|
Make helpers static. NFC.
|
2017-11-24 14:55:41 +00:00 |
|
AMDGPULibFunc.cpp
|
[AMDGPU] Remove hardcoded address space value from AMDGPULibFunc
|
2017-11-04 17:37:43 +00:00 |
|
AMDGPULibFunc.h
|
[AMDGPU] Remove hardcoded address space value from AMDGPULibFunc
|
2017-11-04 17:37:43 +00:00 |
|
AMDGPULowerIntrinsics.cpp
|
Extend memcpy expansion in Transform/Utils to handle wider operand types.
|
2017-07-07 02:00:06 +00:00 |
|
AMDGPUMCInstLower.cpp
|
MachineFunction: Return reference from getFunction(); NFC
|
2017-12-15 22:22:58 +00:00 |
|
AMDGPUMCInstLower.h
|
…
|
|
|
AMDGPUMachineCFGStructurizer.cpp
|
[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
|
2017-12-07 10:40:31 +00:00 |
|
AMDGPUMachineFunction.cpp
|
MachineFunction: Return reference from getFunction(); NFC
|
2017-12-15 22:22:58 +00:00 |
|
AMDGPUMachineFunction.h
|
[NFC] fix trivial typos in document and comments
|
2018-04-14 08:59:00 +00:00 |
|
AMDGPUMachineModuleInfo.cpp
|
AMDGPU: Implement memory model
|
2017-07-21 21:19:23 +00:00 |
|
AMDGPUMachineModuleInfo.h
|
AMDGPU: Handle more than one memory operand in SIMemoryLegalizer
|
2017-09-07 16:14:21 +00:00 |
|
AMDGPUMacroFusion.cpp
|
AMDGPU: Add macro fusion schedule DAG mutation
|
2017-07-06 20:57:05 +00:00 |
|
AMDGPUMacroFusion.h
|
AMDGPU: Add macro fusion schedule DAG mutation
|
2017-07-06 20:57:05 +00:00 |
|
AMDGPUOpenCLEnqueuedBlockLowering.cpp
|
[AMDGPU] Fix lowering enqueue_kernel
|
2018-04-11 14:46:15 +00:00 |
|
AMDGPUOpenCLImageTypeLoweringPass.cpp
|
[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
|
2017-08-08 23:53:55 +00:00 |
|
AMDGPUPTNote.h
|
AMDGPU/NFC: Move AMDGPU specific note types to ELF.h
|
2017-10-12 18:59:54 +00:00 |
|
AMDGPUPromoteAlloca.cpp
|
AMDGPU/SI: Extend promoting alloca to vector to arrays of up to 16 elements
|
2018-02-16 19:14:17 +00:00 |
|
AMDGPURegAsmNames.inc.cpp
|
AMDGPU: Work around build special casing .inc files
|
2017-06-08 19:25:21 +00:00 |
|
AMDGPURegisterBankInfo.cpp
|
AMDGPU/GlobalISel: RegBankSelect for basic int ops
|
2018-03-19 14:07:23 +00:00 |
|
AMDGPURegisterBankInfo.h
|
AMDGPU/GlobalISel: Define instruction mapping for G_OR
|
2018-03-01 21:25:25 +00:00 |
|
AMDGPURegisterBanks.td
|
AMDGPU/GlobalISel: Define InstrMappings for G_ICMP
|
2018-03-01 19:27:10 +00:00 |
|
AMDGPURegisterInfo.cpp
|
AMDGPU: Really implement getFrameRegister
|
2018-03-27 23:26:59 +00:00 |
|
AMDGPURegisterInfo.h
|
[AMDGPU] Return true in enableMultipleCopyHints().
|
2018-02-17 10:00:28 +00:00 |
|
AMDGPURegisterInfo.td
|
AMDGPU: Move INDIRECT_BASE_ADDR definition out of common files
|
2017-07-29 03:44:07 +00:00 |
|
AMDGPURewriteOutArguments.cpp
|
[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
|
2017-08-08 23:53:55 +00:00 |
|
AMDGPUSearchableTables.td
|
AMDGPU: Dimension-aware image intrinsics
|
2018-04-04 10:58:54 +00:00 |
|
AMDGPUSubtarget.cpp
|
AMDGPU: enable 128-bit for local addr space under an option
|
2018-04-10 22:48:23 +00:00 |
|
AMDGPUSubtarget.h
|
AMDGPU: enable 128-bit for local addr space under an option
|
2018-04-10 22:48:23 +00:00 |
|
AMDGPUTargetMachine.cpp
|
AMDGPU: Initialize GlobalISel passes
|
2018-04-09 16:09:13 +00:00 |
|
AMDGPUTargetMachine.h
|
(Re-landing) Expose a TargetMachine::getTargetTransformInfo function
|
2017-12-22 18:21:59 +00:00 |
|
AMDGPUTargetObjectFile.cpp
|
AMDGPU: Fix set but not used warnings related to AMDGPUAS
|
2017-11-01 19:12:38 +00:00 |
|
AMDGPUTargetObjectFile.h
|
…
|
|
|
AMDGPUTargetTransformInfo.cpp
|
AMDGPU: enable 128-bit for local addr space under an option
|
2018-04-10 22:48:23 +00:00 |
|
AMDGPUTargetTransformInfo.h
|
[AMDGPU] Increased vector length for global/constant loads.
|
2018-03-07 17:09:18 +00:00 |
|
AMDGPUUnifyDivergentExitNodes.cpp
|
Transforms: Introduce Transforms/Utils.h rather than spreading the declarations amongst Scalar.h and IPO.h
|
2018-03-28 17:44:36 +00:00 |
|
AMDGPUUnifyMetadata.cpp
|
[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
|
2017-08-10 00:46:15 +00:00 |
|
AMDILCFGStructurizer.cpp
|
Fix layering of MachineValueType.h by moving it from CodeGen to Support
|
2018-03-23 23:58:25 +00:00 |
|
AMDKernelCodeT.h
|
AMDGPU: Remove max_scratch_backing_memory_byte_size from kernel header
|
2018-04-09 20:47:22 +00:00 |
|
BUFInstructions.td
|
[AMDGPU][MC] Enabled instruction TBUFFER_LOAD_FORMAT_XYZ for SI/CI
|
2018-04-04 13:54:55 +00:00 |
|
CMakeLists.txt
|
Consistently sort add_subdirectory calls in lib/Target/*/CMakeLists.txt
|
2018-04-23 12:49:34 +00:00 |
|
CaymanInstructions.td
|
[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
|
2017-12-07 10:40:31 +00:00 |
|
DSInstructions.td
|
[AMDGPU][MC] Added ds_add_src2_f32
|
2018-03-28 16:21:56 +00:00 |
|
EvergreenInstructions.td
|
AMDGPU: Select BFI patterns with 64-bit ints
|
2018-02-07 00:21:34 +00:00 |
|
FLATInstructions.td
|
[AMDGPU][MC][DISASSEMBLER][GFX9] Corrected decoding of GLOBAL/SCRATCH opcodes
|
2017-11-27 17:14:35 +00:00 |
|
GCNHazardRecognizer.cpp
|
[AMDGPU] Add GCNHazardRecognizer::checkInlineAsmHazards() and GCNHazardRecognizer::checkVALUHazardsHelper(). checkInlineAsmHazards() checks INLINEASM for hazards that we particularly care about (so not exhaustive); this patch adds a check for INLINEASM that defs vregs that hold data-to-be stored by immediately preceding store of more than 8 bytes. If the instr were not within an INLINEASM, this scenario would be handled by checkVALUHazard(). Add checkVALUHazardsHelper(), which will be called by both checkVALUHazards() and checkInlineAsmHazards().
|
2017-12-07 20:34:25 +00:00 |
|
GCNHazardRecognizer.h
|
[AMDGPU] Add GCNHazardRecognizer::checkInlineAsmHazards() and GCNHazardRecognizer::checkVALUHazardsHelper(). checkInlineAsmHazards() checks INLINEASM for hazards that we particularly care about (so not exhaustive); this patch adds a check for INLINEASM that defs vregs that hold data-to-be stored by immediately preceding store of more than 8 bytes. If the instr were not within an INLINEASM, this scenario would be handled by checkVALUHazard(). Add checkVALUHazardsHelper(), which will be called by both checkVALUHazards() and checkInlineAsmHazards().
|
2017-12-07 20:34:25 +00:00 |
|
GCNILPSched.cpp
|
AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experimental)
|
2017-11-20 14:35:53 +00:00 |
|
GCNIterativeScheduler.cpp
|
[AMDGPU] Change std::sort to llvm::sort in response to r327219
|
2018-03-24 17:15:04 +00:00 |
|
GCNIterativeScheduler.h
|
AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experimental)
|
2017-11-20 14:35:53 +00:00 |
|
GCNMinRegStrategy.cpp
|
[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
|
2017-08-08 23:53:55 +00:00 |
|
GCNProcessors.td
|
AMDGPU: Bring processors and features in sync with the spec
|
2018-02-16 21:26:25 +00:00 |
|
GCNRegPressure.cpp
|
Rename LiveIntervalAnalysis.h to LiveIntervals.h
|
2017-12-13 02:51:04 +00:00 |
|
GCNRegPressure.h
|
Rename LiveIntervalAnalysis.h to LiveIntervals.h
|
2017-12-13 02:51:04 +00:00 |
|
GCNSchedStrategy.cpp
|
[NFC] fix trivial typos in comments
|
2018-01-22 05:54:46 +00:00 |
|
GCNSchedStrategy.h
|
fix typos in comments and error messges; NFC
|
2017-07-13 06:48:39 +00:00 |
|
LLVMBuild.txt
|
…
|
|
|
MIMGInstructions.td
|
[AMDGPU][MC] Added support of 3-element addresses for MIMG instructions
|
2018-04-04 13:01:17 +00:00 |
|
R600ClauseMergePass.cpp
|
MachineFunction: Return reference from getFunction(); NFC
|
2017-12-15 22:22:58 +00:00 |
|
R600ControlFlowFinalizer.cpp
|
MachineFunction: Return reference from getFunction(); NFC
|
2017-12-15 22:22:58 +00:00 |
|
R600Defines.h
|
…
|
|
|
R600EmitClauseMarkers.cpp
|
Sort the remaining #include lines in include/... and lib/....
|
2017-06-06 11:49:48 +00:00 |
|
R600ExpandSpecialInstrs.cpp
|
[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
|
2017-08-10 00:46:15 +00:00 |
|
R600FrameLowering.cpp
|
Sort the remaining #include lines in include/... and lib/....
|
2017-06-06 11:49:48 +00:00 |
|
R600FrameLowering.h
|
AMDGPU: Initial implementation of calls
|
2017-08-01 19:54:18 +00:00 |
|
R600ISelLowering.cpp
|
Fix layering of MachineValueType.h by moving it from CodeGen to Support
|
2018-03-23 23:58:25 +00:00 |
|
R600ISelLowering.h
|
Add DAG argument to canMergeStoresTo NFC.
|
2017-07-10 20:25:54 +00:00 |
|
R600InstrFormats.td
|
AMDGPU: Remove global isGCN predicates
|
2017-10-03 00:06:41 +00:00 |
|
R600InstrInfo.cpp
|
[AMDGPU] Make sure all super regs of reserved regs are marked reserved.
|
2018-01-24 18:09:53 +00:00 |
|
R600InstrInfo.h
|
[AMDGPU] Make sure all super regs of reserved regs are marked reserved.
|
2018-01-24 18:09:53 +00:00 |
|
R600Instructions.td
|
AMDGPU: Move ADDRIndirect complex pattern into R600Instructions.td
|
2018-01-29 23:29:26 +00:00 |
|
R600Intrinsics.td
|
…
|
|
|
R600MachineFunctionInfo.cpp
|
…
|
|
|
R600MachineFunctionInfo.h
|
…
|
|
|
R600MachineScheduler.cpp
|
[CodeGen] Rename DEBUG_TYPE to match passnames
|
2017-07-11 22:08:28 +00:00 |
|
R600MachineScheduler.h
|
…
|
|
|
R600OptimizeVectorRegisters.cpp
|
MachineFunction: Return reference from getFunction(); NFC
|
2017-12-15 22:22:58 +00:00 |
|
R600Packetizer.cpp
|
AMDGPU/R600: Initialize more passes
|
2017-08-02 22:19:45 +00:00 |
|
R600Processors.td
|
AMDGPU/EG: Add a new FeatureFMA and use it to selectively enable FMA instruction
|
2017-12-04 23:07:28 +00:00 |
|
R600RegisterInfo.cpp
|
[AMDGPU] Make sure all super regs of reserved regs are marked reserved.
|
2018-01-24 18:09:53 +00:00 |
|
R600RegisterInfo.h
|
AMDGPU: Start defining a calling convention
|
2017-05-17 21:56:25 +00:00 |
|
R600RegisterInfo.td
|
AMDGPU: Move INDIRECT_BASE_ADDR definition out of common files
|
2017-07-29 03:44:07 +00:00 |
|
R600Schedule.td
|
…
|
|
|
R700Instructions.td
|
…
|
|
|
SIAnnotateControlFlow.cpp
|
Fix a couple of layering violations in Transforms
|
2018-03-21 22:34:23 +00:00 |
|
SIDebuggerInsertNops.cpp
|
Sort the remaining #include lines in include/... and lib/....
|
2017-06-06 11:49:48 +00:00 |
|
SIDefines.h
|
AMDGPU: Assign enum name to stack ID
|
2018-04-23 15:51:26 +00:00 |
|
SIFixSGPRCopies.cpp
|
[CodeGen] Unify MBB reference format in both MIR and debug output
|
2017-12-04 17:18:51 +00:00 |
|
SIFixVGPRCopies.cpp
|
…
|
|
|
SIFixWWMLiveness.cpp
|
Rename LiveIntervalAnalysis.h to LiveIntervals.h
|
2017-12-13 02:51:04 +00:00 |
|
SIFoldOperands.cpp
|
[AMDGPU] Use packed literals with zero either lower or hi part
|
2018-04-19 21:16:50 +00:00 |
|
SIFrameLowering.cpp
|
AMDGPU: Assign enum name to stack ID
|
2018-04-23 15:51:26 +00:00 |
|
SIFrameLowering.h
|
[AMDGPU] AMDPAL scratch buffer support
|
2017-09-29 09:49:35 +00:00 |
|
SIISelLowering.cpp
|
[NFC] fix trivial typos in comments
|
2018-04-13 11:37:06 +00:00 |
|
SIISelLowering.h
|
AMDGPU/SI: Add d16 support for buffer intrinsics.
|
2018-01-12 21:12:19 +00:00 |
|
SIInsertSkips.cpp
|
Fix compiler warning introduced in r325931. NFC.
|
2018-02-23 19:11:33 +00:00 |
|
SIInsertWaitcnts.cpp
|
[AMDGPU][Waitcnt] NFC. Cleanup some code/naming consistency:
|
2018-04-24 15:59:59 +00:00 |
|
SIInsertWaits.cpp
|
[NFC] fix trivial typos in comments
|
2018-02-22 07:48:29 +00:00 |
|
SIInstrFormats.td
|
[MachineOperand][Target] MachineOperand::isRenamable semantics changes
|
2018-02-23 18:25:08 +00:00 |
|
SIInstrInfo.cpp
|
AMDGPU: Move a flawed assert when spilling SGPRs
|
2018-04-23 16:13:30 +00:00 |
|
SIInstrInfo.h
|
[AMDGPU][MC] Added lds support for MUBUF instructions
|
2018-02-21 13:13:48 +00:00 |
|
SIInstrInfo.td
|
AMDGPU: Dimension-aware image intrinsics
|
2018-04-04 10:58:54 +00:00 |
|
SIInstructions.td
|
[AMDGPU][MC][GFX8][GFX9][DISASSEMBLER] Added "_e32" suffix to 32-bit VINTRP opcodes
|
2018-03-16 16:38:04 +00:00 |
|
SIIntrinsics.td
|
…
|
|
|
SILoadStoreOptimizer.cpp
|
AMDGPU: Track physreg uses in SILoadStoreOptimizer
|
2018-02-23 10:45:56 +00:00 |
|
SILowerControlFlow.cpp
|
Rename LiveIntervalAnalysis.h to LiveIntervals.h
|
2017-12-13 02:51:04 +00:00 |
|
SILowerI1Copies.cpp
|
AMDGPU: Fix copying i1 value out of loop with non-uniform exit
|
2018-04-04 10:57:58 +00:00 |
|
SIMachineFunctionInfo.cpp
|
AMDGPU: Fix not preserving CSR VGPR if used for SGPR spills
|
2018-03-27 19:42:55 +00:00 |
|
SIMachineFunctionInfo.h
|
AMDGPU: Support realigning stack
|
2018-03-29 21:30:06 +00:00 |
|
SIMachineScheduler.cpp
|
[MachineScheduler] NFC refactoring
|
2018-04-12 07:21:39 +00:00 |
|
SIMachineScheduler.h
|
AMDGPU/SI: Force exports at the end for SI scheduler
|
2017-07-25 20:36:58 +00:00 |
|
SIMemoryLegalizer.cpp
|
[AMDGPU] More descriptive names in the memory legalizer
|
2018-02-09 06:05:33 +00:00 |
|
SIOptimizeExecMasking.cpp
|
AMDGPU: Fix a corner case crash in SIOptimizeExecMasking
|
2018-04-23 13:05:50 +00:00 |
|
SIOptimizeExecMaskingPreRA.cpp
|
MachineFunction: Return reference from getFunction(); NFC
|
2017-12-15 22:22:58 +00:00 |
|
SIPeepholeSDWA.cpp
|
AMDGPU: Fix SDWA peephole for V_AND_B32
|
2018-04-23 13:06:03 +00:00 |
|
SIRegisterInfo.cpp
|
AMDGPU: Move a flawed assert when spilling SGPRs
|
2018-04-23 16:13:30 +00:00 |
|
SIRegisterInfo.h
|
[AMDGPU] Make sure all super regs of reserved regs are marked reserved.
|
2018-01-24 18:09:53 +00:00 |
|
SIRegisterInfo.td
|
[AMDGPU][MC][GFX8][GFX9] Added XNACK_MASK support
|
2018-01-10 14:22:19 +00:00 |
|
SISchedule.td
|
[SchedModel] Complete models shouldn't match against itineraries when they don't use them (PR35639)
|
2018-04-05 13:11:36 +00:00 |
|
SIShrinkInstructions.cpp
|
[NFC] fix trivial typos in comments
|
2018-04-13 11:37:06 +00:00 |
|
SIWholeQuadMode.cpp
|
MachineFunction: Return reference from getFunction(); NFC
|
2017-12-15 22:22:58 +00:00 |
|
SMInstructions.td
|
[AMDGPU][MC][VI][GFX9] Added s_atc_probe* instructions
|
2018-04-06 15:48:39 +00:00 |
|
SOPInstructions.td
|
[AMDGPU][MC][GFX9] Added instructions s_mul_hi_*32, s_lshl*_add_u32
|
2018-04-09 13:10:33 +00:00 |
|
VIInstrFormats.td
|
…
|
|
|
VIInstructions.td
|
…
|
|
|
VOP1Instructions.td
|
[AMDGPU][MC][GFX9] Added v_screen_partition_4se_b32
|
2018-04-11 13:13:30 +00:00 |
|
VOP2Instructions.td
|
[AMDGPU][MC][VI][GFX9] Added support of SDWA/DPP for v_cndmask_b32
|
2018-04-16 12:41:38 +00:00 |
|
VOP3Instructions.td
|
[AMDGPU] Fixed some instructions latencies
|
2018-03-30 16:19:13 +00:00 |
|
VOP3PInstructions.td
|
AMDGPU: Introduce common SOP_Pseudo and VOP_Pseudo TableGen base classes
|
2018-03-26 13:56:53 +00:00 |
|
VOPCInstructions.td
|
[AMDGPU][MC] Corrected default values for unused SDWA operands
|
2018-03-16 15:40:27 +00:00 |
|
VOPInstructions.td
|
AMDGPU: Introduce common SOP_Pseudo and VOP_Pseudo TableGen base classes
|
2018-03-26 13:56:53 +00:00 |
70901b9047