Sebastian Neubauer 409a2f0f9e [AMDGPU] Allow no saddr for global addtid insts ... I think the global_load/store_dword_addtid instructions support switching off the scalar address. Add assembler and disassembler support for this. Differential Revision: https://reviews.llvm.org/D93288		2020-12-16 10:01:40 +01:00
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AArch64	[ARM][AArch64] Adding Neoverse N2 CPU support	2020-11-25 11:42:54 +00:00
AMDGPU	[AMDGPU] Allow no saddr for global addtid insts	2020-12-16 10:01:40 +01:00
ARC	…
ARM	[ARM] Fix Asm/Disasm of TBB/TBH instructions	2020-07-22 09:31:56 +01:00
Hexagon	…
Lanai	…
MSP430	…
Mips	[mips] Add tests to check disassembling of add.ps/mul.ps/sub.ps instructions	2020-11-13 14:31:12 +03:00
PowerPC	[PowerPC] Add outer product instructions for MMA	2020-09-30 18:06:49 -05:00
RISCV	[RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump	2020-12-04 10:34:12 -08:00
Sparc	…
SystemZ	…
WebAssembly	[WebAssembly] Renumber SIMD opcodes	2020-05-01 17:20:49 -07:00
X86	[X86] Support Intel avxvnni	2020-10-31 12:39:51 +08:00
XCore	…