llvm-project/llvm/test/MC
Fangrui Song 66bcbdbc9c [AArch64InstPrinter] Change printADRPLabel to print the target address in hexadecimal form
Similar to D77853. Change ADRP to print the target address in hex, instead of the raw immediate.
The behavior is similar to GNU objdump but we also include `0x`.

Note: GNU objdump is not consistent whether or not to emit `0x` for different architectures. We try emitting 0x consistently for all targets.

```
GNU objdump:       adrp x16, 10000000
Old llvm-objdump:  adrp x16, #0
New llvm-objdump:  adrp x16, 0x10000000
```

`adrp Xd, 0x...` assembles to a relocation referencing `*ABS*+0x10000` which is not intended. We need to use a linker or use yaml2obj.
The main test is `test/tools/llvm-objdump/ELF/AArch64/pcrel-address.yaml`

Differential Revision: https://reviews.llvm.org/D93241
2020-12-16 09:20:55 -08:00
..
AArch64 [AArch64InstPrinter] Change printADRPLabel to print the target address in hexadecimal form 2020-12-16 09:20:55 -08:00
AMDGPU [AMDGPU] Allow no saddr for global addtid insts 2020-12-16 10:01:40 +01:00
ARM [llvm-readobj] - For SHT_REL relocations, don't display an addend. 2020-12-14 12:03:00 +03:00
AVR [AVRInstPrinter] printOperand: support llvm-objdump --print-imm-hex 2020-07-12 08:14:52 -07:00
AsmParser [MC] Fix ICE with non-newline terminated input 2020-12-09 23:39:32 +00:00
BPF [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
COFF [CodeView] Fix inline sites that are missing code offsets. 2020-12-07 13:01:53 -08:00
Disassembler [AMDGPU] Allow no saddr for global addtid insts 2020-12-16 10:01:40 +01:00
ELF [llvm-readobj] - For SHT_REL relocations, don't display an addend. 2020-12-14 12:03:00 +03:00
Hexagon [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
Lanai
MSP430 [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
MachO [Triple][MachO] Define "arm64e", an AArch64 subarch for Pointer Auth. 2020-12-03 07:53:59 -08:00
Mips [llvm-readobj] - For SHT_REL relocations, don't display an addend. 2020-12-14 12:03:00 +03:00
PowerPC [PowerPC] Correct the bit-width definition for some imm operand in td. 2020-12-08 03:20:12 +00:00
RISCV [RISCV] Prevent assertion in the assembler if vmerge or vfmerge are given a V0 destination. 2020-12-14 17:22:55 -08:00
Sparc [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
SystemZ [SystemZ] Adding extra extended mnemonics for SystemZ target 2020-12-02 08:25:31 -05:00
VE [VE] Add missing BCR format 2020-10-29 23:30:49 +09:00
WebAssembly [WebAssembly] Support COMDAT sections in assembly syntax 2020-12-10 16:43:59 -08:00
X86 [X86] Add REX prefix for GOTTPOFF/TLSDESC relocs in x32 mode 2020-12-15 23:07:34 +00:00