Mogball 7c5ecc8b7e [mlir][vector] Insert/extract element can accept index ... `vector::InsertElementOp` and `vector::ExtractElementOp` have had their `position` operand changed to accept `AnySignlessIntegerOrIndex` for better operability with operations that use `index`, such as affine loops. LLVM's `extractelement` and `insertelement` can also accept `i64`, so lowering directly to these operations without explicitly inserting casts is allowed. SPIRV's equivalent ops can also accept `i64`. Reviewed By: nicolasvasilache, jpienaar Differential Revision: https://reviews.llvm.org/D114139		2021-11-18 22:40:29 +00:00
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vector-mask-to-llvm.mlir	[MLIR] Replace std ops with arith dialect ops	2021-10-13 03:07:03 +00:00
vector-reduction-to-llvm.mlir	[mlir] make vector to llvm conversion truly partial	2021-02-04 11:33:24 +01:00
vector-to-llvm.mlir	[mlir][vector] Insert/extract element can accept index	2021-11-18 22:40:29 +00:00