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llvm-project/mlir/lib/Dialect/Affine/Transforms
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Uday Bondhugula 54384d1723 [MLIR] Make store to load fwd condition less conservative 
Make store to load fwd condition for -memref-dataflow-opt less
conservative. Post dominance info is not really needed. Add additional
check for common cases.

Differential Revision: https://reviews.llvm.org/D104174
 		2021-06-17 01:26:38 +05:30
..
AffineDataCopyGeneration.cpp [WIP][mlir] Resolve memref dependency in canonicalize pass. 2021-05-17 11:33:38 +02:00
AffineLoopInvariantCodeMotion.cpp [MLIR][Affine][LICM] Mark users of `iter_args` variant 2021-05-25 15:56:52 +05:30
AffineLoopNormalize.cpp [mlir] make normalizeAffineFor public 2021-06-11 20:12:37 -07:00
AffineParallelize.cpp [MLIR] Fix affine parallelize pass. 2021-06-17 01:25:24 +05:30
AffineScalarReplacement.cpp [MLIR] Make store to load fwd condition less conservative 2021-06-17 01:26:38 +05:30
CMakeLists.txt [MLIR][NFC] Rename MemRefDataFlow -> AffineScalarReplacement 2021-06-14 17:52:53 +05:30
LoopTiling.cpp [mlir] Mark LogicalResult as LLVM_NODISCARD 2021-02-04 15:10:10 -08:00
LoopUnroll.cpp [mlir] Mark LogicalResult as LLVM_NODISCARD 2021-02-04 15:10:10 -08:00
LoopUnrollAndJam.cpp [mlir] Mark LogicalResult as LLVM_NODISCARD 2021-02-04 15:10:10 -08:00
PassDetail.h [MLIR] Create memref dialect and move dialect-specific ops from std. 2021-03-15 11:14:09 +01:00
SimplifyAffineStructures.cpp Rename FrozenRewritePatternList -> FrozenRewritePatternSet; NFC. 2021-03-22 17:40:45 -07:00
SuperVectorize.cpp [mlir][Affine][Vector] Support vectorizing reduction loops 2021-05-05 09:03:59 -07:00