Hao Liu 99eac7ee44 Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). ... Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4). llvm-svn: 192361		2013-10-10 17:00:52 +00:00
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AArch64	Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem).	2013-10-10 17:00:52 +00:00
ARM	ARM: correct liveness flags during ARMLoadStoreOpt	2013-10-10 09:28:20 +00:00
CPP	[tests] Cleanup initialization of test suffixes.	2013-08-16 00:37:11 +00:00
Generic	Change objectsize intrinsic to accept different address spaces.	2013-10-07 18:06:48 +00:00
Hexagon	TBAA: remove !tbaa from testing cases when they are not needed.	2013-09-30 18:17:35 +00:00
Inputs	Debug Info: add an identifier field to DICompositeType.	2013-08-26 22:39:55 +00:00
MSP430	[tests] Cleanup initialization of test suffixes.	2013-08-16 00:37:11 +00:00
Mips	[mips] Do not generate INS/EXT nodes if target does not have support for	2013-10-09 23:36:17 +00:00
NVPTX	[NVPTX] Make constant vector test case endian-independent	2013-09-19 13:14:44 +00:00
PowerPC	TBAA: update tbaa format from scalar format to struct-path aware format.	2013-09-30 18:17:55 +00:00
R600	Add some xfaild R600 tests.	2013-10-08 18:06:36 +00:00
SPARC	[Sparc] Disable tail call optimization for sparc64.	2013-10-09 12:50:39 +00:00
SystemZ	[SystemZ] Add comparisons of high words and memory	2013-10-01 15:00:44 +00:00
Thumb	ARM: Use "dmb sy" for barriers on M-class CPUs	2013-08-28 14:39:19 +00:00
Thumb2	Fix spelling intruction -> instruction.	2013-09-28 11:46:15 +00:00
X86	Disable function padding to get this test to pass on atom.	2013-10-10 12:46:23 +00:00
XCore	XCore handling of thread local lowering	2013-09-09 10:42:11 +00:00