forked from OSchip/llvm-project
472 lines
15 KiB
C++
472 lines
15 KiB
C++
//===- ExecutionDomainFix.cpp - Fix execution domain issues ----*- C++ -*--===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/ExecutionDomainFix.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "execution-deps-fix"
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iterator_range<SmallVectorImpl<int>::const_iterator>
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ExecutionDomainFix::regIndices(unsigned Reg) const {
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assert(Reg < AliasMap.size() && "Invalid register");
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const auto &Entry = AliasMap[Reg];
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return make_range(Entry.begin(), Entry.end());
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}
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DomainValue *ExecutionDomainFix::alloc(int domain) {
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DomainValue *dv = Avail.empty() ? new (Allocator.Allocate()) DomainValue
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: Avail.pop_back_val();
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if (domain >= 0)
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dv->addDomain(domain);
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assert(dv->Refs == 0 && "Reference count wasn't cleared");
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assert(!dv->Next && "Chained DomainValue shouldn't have been recycled");
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return dv;
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}
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void ExecutionDomainFix::release(DomainValue *DV) {
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while (DV) {
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assert(DV->Refs && "Bad DomainValue");
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if (--DV->Refs)
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return;
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// There are no more DV references. Collapse any contained instructions.
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if (DV->AvailableDomains && !DV->isCollapsed())
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collapse(DV, DV->getFirstDomain());
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DomainValue *Next = DV->Next;
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DV->clear();
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Avail.push_back(DV);
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// Also release the next DomainValue in the chain.
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DV = Next;
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}
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}
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DomainValue *ExecutionDomainFix::resolve(DomainValue *&DVRef) {
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DomainValue *DV = DVRef;
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if (!DV || !DV->Next)
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return DV;
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// DV has a chain. Find the end.
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do
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DV = DV->Next;
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while (DV->Next);
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// Update DVRef to point to DV.
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retain(DV);
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release(DVRef);
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DVRef = DV;
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return DV;
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}
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void ExecutionDomainFix::setLiveReg(int rx, DomainValue *dv) {
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assert(unsigned(rx) < NumRegs && "Invalid index");
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assert(!LiveRegs.empty() && "Must enter basic block first.");
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if (LiveRegs[rx] == dv)
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return;
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if (LiveRegs[rx])
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release(LiveRegs[rx]);
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LiveRegs[rx] = retain(dv);
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}
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void ExecutionDomainFix::kill(int rx) {
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assert(unsigned(rx) < NumRegs && "Invalid index");
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assert(!LiveRegs.empty() && "Must enter basic block first.");
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if (!LiveRegs[rx])
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return;
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release(LiveRegs[rx]);
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LiveRegs[rx] = nullptr;
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}
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void ExecutionDomainFix::force(int rx, unsigned domain) {
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assert(unsigned(rx) < NumRegs && "Invalid index");
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assert(!LiveRegs.empty() && "Must enter basic block first.");
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if (DomainValue *dv = LiveRegs[rx]) {
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if (dv->isCollapsed())
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dv->addDomain(domain);
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else if (dv->hasDomain(domain))
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collapse(dv, domain);
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else {
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// This is an incompatible open DomainValue. Collapse it to whatever and
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// force the new value into domain. This costs a domain crossing.
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collapse(dv, dv->getFirstDomain());
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assert(LiveRegs[rx] && "Not live after collapse?");
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LiveRegs[rx]->addDomain(domain);
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}
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} else {
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// Set up basic collapsed DomainValue.
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setLiveReg(rx, alloc(domain));
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}
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}
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void ExecutionDomainFix::collapse(DomainValue *dv, unsigned domain) {
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assert(dv->hasDomain(domain) && "Cannot collapse");
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// Collapse all the instructions.
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while (!dv->Instrs.empty())
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TII->setExecutionDomain(*dv->Instrs.pop_back_val(), domain);
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dv->setSingleDomain(domain);
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// If there are multiple users, give them new, unique DomainValues.
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if (!LiveRegs.empty() && dv->Refs > 1)
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for (unsigned rx = 0; rx != NumRegs; ++rx)
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if (LiveRegs[rx] == dv)
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setLiveReg(rx, alloc(domain));
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}
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bool ExecutionDomainFix::merge(DomainValue *A, DomainValue *B) {
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assert(!A->isCollapsed() && "Cannot merge into collapsed");
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assert(!B->isCollapsed() && "Cannot merge from collapsed");
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if (A == B)
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return true;
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// Restrict to the domains that A and B have in common.
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unsigned common = A->getCommonDomains(B->AvailableDomains);
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if (!common)
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return false;
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A->AvailableDomains = common;
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A->Instrs.append(B->Instrs.begin(), B->Instrs.end());
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// Clear the old DomainValue so we won't try to swizzle instructions twice.
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B->clear();
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// All uses of B are referred to A.
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B->Next = retain(A);
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for (unsigned rx = 0; rx != NumRegs; ++rx) {
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assert(!LiveRegs.empty() && "no space allocated for live registers");
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if (LiveRegs[rx] == B)
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setLiveReg(rx, A);
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}
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return true;
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}
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void ExecutionDomainFix::enterBasicBlock(
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const LoopTraversal::TraversedMBBInfo &TraversedMBB) {
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MachineBasicBlock *MBB = TraversedMBB.MBB;
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// Set up LiveRegs to represent registers entering MBB.
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// Set default domain values to 'no domain' (nullptr)
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if (LiveRegs.empty())
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LiveRegs.assign(NumRegs, nullptr);
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// This is the entry block.
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if (MBB->pred_empty()) {
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LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << ": entry\n");
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return;
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}
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// Try to coalesce live-out registers from predecessors.
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for (MachineBasicBlock *pred : MBB->predecessors()) {
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assert(unsigned(pred->getNumber()) < MBBOutRegsInfos.size() &&
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"Should have pre-allocated MBBInfos for all MBBs");
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LiveRegsDVInfo &Incoming = MBBOutRegsInfos[pred->getNumber()];
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// Incoming is null if this is a backedge from a BB
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// we haven't processed yet
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if (Incoming.empty())
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continue;
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for (unsigned rx = 0; rx != NumRegs; ++rx) {
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DomainValue *pdv = resolve(Incoming[rx]);
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if (!pdv)
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continue;
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if (!LiveRegs[rx]) {
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setLiveReg(rx, pdv);
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continue;
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}
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// We have a live DomainValue from more than one predecessor.
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if (LiveRegs[rx]->isCollapsed()) {
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// We are already collapsed, but predecessor is not. Force it.
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unsigned Domain = LiveRegs[rx]->getFirstDomain();
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if (!pdv->isCollapsed() && pdv->hasDomain(Domain))
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collapse(pdv, Domain);
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continue;
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}
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// Currently open, merge in predecessor.
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if (!pdv->isCollapsed())
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merge(LiveRegs[rx], pdv);
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else
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force(rx, pdv->getFirstDomain());
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}
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}
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LLVM_DEBUG(dbgs() << printMBBReference(*MBB)
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<< (!TraversedMBB.IsDone ? ": incomplete\n"
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: ": all preds known\n"));
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}
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void ExecutionDomainFix::leaveBasicBlock(
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const LoopTraversal::TraversedMBBInfo &TraversedMBB) {
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assert(!LiveRegs.empty() && "Must enter basic block first.");
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unsigned MBBNumber = TraversedMBB.MBB->getNumber();
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assert(MBBNumber < MBBOutRegsInfos.size() &&
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"Unexpected basic block number.");
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// Save register clearances at end of MBB - used by enterBasicBlock().
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for (DomainValue *OldLiveReg : MBBOutRegsInfos[MBBNumber]) {
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release(OldLiveReg);
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}
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MBBOutRegsInfos[MBBNumber] = LiveRegs;
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LiveRegs.clear();
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}
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bool ExecutionDomainFix::visitInstr(MachineInstr *MI) {
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// Update instructions with explicit execution domains.
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std::pair<uint16_t, uint16_t> DomP = TII->getExecutionDomain(*MI);
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if (DomP.first) {
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if (DomP.second)
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visitSoftInstr(MI, DomP.second);
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else
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visitHardInstr(MI, DomP.first);
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}
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return !DomP.first;
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}
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void ExecutionDomainFix::processDefs(MachineInstr *MI, bool Kill) {
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assert(!MI->isDebugInstr() && "Won't process debug values");
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const MCInstrDesc &MCID = MI->getDesc();
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for (unsigned i = 0,
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e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
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i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg())
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continue;
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if (MO.isUse())
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continue;
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for (int rx : regIndices(MO.getReg())) {
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// This instruction explicitly defines rx.
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LLVM_DEBUG(dbgs() << printReg(RC->getRegister(rx), TRI) << ":\t" << *MI);
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// Kill off domains redefined by generic instructions.
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if (Kill)
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kill(rx);
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}
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}
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}
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void ExecutionDomainFix::visitHardInstr(MachineInstr *mi, unsigned domain) {
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// Collapse all uses.
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for (unsigned i = mi->getDesc().getNumDefs(),
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e = mi->getDesc().getNumOperands();
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i != e; ++i) {
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MachineOperand &mo = mi->getOperand(i);
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if (!mo.isReg())
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continue;
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for (int rx : regIndices(mo.getReg())) {
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force(rx, domain);
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}
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}
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// Kill all defs and force them.
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for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) {
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MachineOperand &mo = mi->getOperand(i);
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if (!mo.isReg())
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continue;
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for (int rx : regIndices(mo.getReg())) {
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kill(rx);
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force(rx, domain);
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}
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}
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}
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void ExecutionDomainFix::visitSoftInstr(MachineInstr *mi, unsigned mask) {
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// Bitmask of available domains for this instruction after taking collapsed
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// operands into account.
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unsigned available = mask;
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// Scan the explicit use operands for incoming domains.
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SmallVector<int, 4> used;
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if (!LiveRegs.empty())
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for (unsigned i = mi->getDesc().getNumDefs(),
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e = mi->getDesc().getNumOperands();
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i != e; ++i) {
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MachineOperand &mo = mi->getOperand(i);
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if (!mo.isReg())
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continue;
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for (int rx : regIndices(mo.getReg())) {
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DomainValue *dv = LiveRegs[rx];
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if (dv == nullptr)
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continue;
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// Bitmask of domains that dv and available have in common.
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unsigned common = dv->getCommonDomains(available);
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// Is it possible to use this collapsed register for free?
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if (dv->isCollapsed()) {
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// Restrict available domains to the ones in common with the operand.
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// If there are no common domains, we must pay the cross-domain
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// penalty for this operand.
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if (common)
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available = common;
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} else if (common)
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// Open DomainValue is compatible, save it for merging.
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used.push_back(rx);
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else
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// Open DomainValue is not compatible with instruction. It is useless
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// now.
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kill(rx);
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}
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}
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// If the collapsed operands force a single domain, propagate the collapse.
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if (isPowerOf2_32(available)) {
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unsigned domain = countTrailingZeros(available);
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TII->setExecutionDomain(*mi, domain);
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visitHardInstr(mi, domain);
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return;
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}
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// Kill off any remaining uses that don't match available, and build a list of
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// incoming DomainValues that we want to merge.
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SmallVector<int, 4> Regs;
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for (int rx : used) {
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assert(!LiveRegs.empty() && "no space allocated for live registers");
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DomainValue *&LR = LiveRegs[rx];
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// This useless DomainValue could have been missed above.
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if (!LR->getCommonDomains(available)) {
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kill(rx);
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continue;
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}
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// Sorted insertion.
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// Enables giving priority to the latest domains during merging.
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const int Def = RDA->getReachingDef(mi, RC->getRegister(rx));
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auto I = llvm::bsearch(Regs, [&](int I) {
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return Def < RDA->getReachingDef(mi, RC->getRegister(I));
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});
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Regs.insert(I, rx);
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}
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// doms are now sorted in order of appearance. Try to merge them all, giving
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// priority to the latest ones.
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DomainValue *dv = nullptr;
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while (!Regs.empty()) {
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if (!dv) {
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dv = LiveRegs[Regs.pop_back_val()];
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// Force the first dv to match the current instruction.
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dv->AvailableDomains = dv->getCommonDomains(available);
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assert(dv->AvailableDomains && "Domain should have been filtered");
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continue;
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}
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DomainValue *Latest = LiveRegs[Regs.pop_back_val()];
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// Skip already merged values.
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if (Latest == dv || Latest->Next)
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continue;
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if (merge(dv, Latest))
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continue;
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// If latest didn't merge, it is useless now. Kill all registers using it.
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for (int i : used) {
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assert(!LiveRegs.empty() && "no space allocated for live registers");
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if (LiveRegs[i] == Latest)
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kill(i);
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}
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}
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// dv is the DomainValue we are going to use for this instruction.
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if (!dv) {
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dv = alloc();
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dv->AvailableDomains = available;
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}
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dv->Instrs.push_back(mi);
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// Finally set all defs and non-collapsed uses to dv. We must iterate through
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// all the operators, including imp-def ones.
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for (MachineOperand &mo : mi->operands()) {
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if (!mo.isReg())
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continue;
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for (int rx : regIndices(mo.getReg())) {
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if (!LiveRegs[rx] || (mo.isDef() && LiveRegs[rx] != dv)) {
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kill(rx);
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setLiveReg(rx, dv);
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}
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}
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}
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}
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void ExecutionDomainFix::processBasicBlock(
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const LoopTraversal::TraversedMBBInfo &TraversedMBB) {
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enterBasicBlock(TraversedMBB);
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// If this block is not done, it makes little sense to make any decisions
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// based on clearance information. We need to make a second pass anyway,
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// and by then we'll have better information, so we can avoid doing the work
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// to try and break dependencies now.
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for (MachineInstr &MI : *TraversedMBB.MBB) {
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if (!MI.isDebugInstr()) {
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bool Kill = false;
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if (TraversedMBB.PrimaryPass)
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Kill = visitInstr(&MI);
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processDefs(&MI, Kill);
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}
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}
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leaveBasicBlock(TraversedMBB);
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}
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bool ExecutionDomainFix::runOnMachineFunction(MachineFunction &mf) {
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if (skipFunction(mf.getFunction()))
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return false;
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MF = &mf;
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TII = MF->getSubtarget().getInstrInfo();
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TRI = MF->getSubtarget().getRegisterInfo();
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LiveRegs.clear();
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assert(NumRegs == RC->getNumRegs() && "Bad regclass");
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LLVM_DEBUG(dbgs() << "********** FIX EXECUTION DOMAIN: "
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<< TRI->getRegClassName(RC) << " **********\n");
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// If no relevant registers are used in the function, we can skip it
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// completely.
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bool anyregs = false;
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const MachineRegisterInfo &MRI = mf.getRegInfo();
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for (unsigned Reg : *RC) {
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if (MRI.isPhysRegUsed(Reg)) {
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anyregs = true;
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break;
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}
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}
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if (!anyregs)
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return false;
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RDA = &getAnalysis<ReachingDefAnalysis>();
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// Initialize the AliasMap on the first use.
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if (AliasMap.empty()) {
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// Given a PhysReg, AliasMap[PhysReg] returns a list of indices into RC and
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// therefore the LiveRegs array.
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AliasMap.resize(TRI->getNumRegs());
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for (unsigned i = 0, e = RC->getNumRegs(); i != e; ++i)
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for (MCRegAliasIterator AI(RC->getRegister(i), TRI, true); AI.isValid();
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++AI)
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AliasMap[*AI].push_back(i);
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}
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// Initialize the MBBOutRegsInfos
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MBBOutRegsInfos.resize(mf.getNumBlockIDs());
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// Traverse the basic blocks.
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LoopTraversal Traversal;
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LoopTraversal::TraversalOrder TraversedMBBOrder = Traversal.traverse(mf);
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for (LoopTraversal::TraversedMBBInfo TraversedMBB : TraversedMBBOrder) {
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processBasicBlock(TraversedMBB);
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}
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for (LiveRegsDVInfo OutLiveRegs : MBBOutRegsInfos) {
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for (DomainValue *OutLiveReg : OutLiveRegs) {
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if (OutLiveReg)
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release(OutLiveReg);
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}
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}
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MBBOutRegsInfos.clear();
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Avail.clear();
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Allocator.DestroyAll();
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return false;
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}
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