forked from OSchip/llvm-project
405 lines
11 KiB
C++
405 lines
11 KiB
C++
#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MIRParser/MIRParser.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/IR/LegacyPassManager.h"
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#include "llvm/Support/MemoryBuffer.h"
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#include "llvm/Support/SourceMgr.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/TargetSelect.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "gtest/gtest.h"
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using namespace llvm;
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namespace llvm {
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void initializeTestPassPass(PassRegistry &);
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}
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namespace {
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void initLLVM() {
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InitializeAllTargets();
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InitializeAllTargetMCs();
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InitializeAllAsmPrinters();
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InitializeAllAsmParsers();
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PassRegistry *Registry = PassRegistry::getPassRegistry();
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initializeCore(*Registry);
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initializeCodeGen(*Registry);
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}
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/// Create a TargetMachine. As we lack a dedicated always available target for
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/// unittests, we go for "AMDGPU" to be able to test normal and subregister
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/// liveranges.
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std::unique_ptr<TargetMachine> createTargetMachine() {
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Triple TargetTriple("amdgcn--");
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std::string Error;
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const Target *T = TargetRegistry::lookupTarget("", TargetTriple, Error);
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if (!T)
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return nullptr;
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TargetOptions Options;
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return std::unique_ptr<TargetMachine>(T->createTargetMachine(
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"AMDGPU", "", "", Options, None, None, CodeGenOpt::Aggressive));
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}
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std::unique_ptr<Module> parseMIR(LLVMContext &Context,
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legacy::PassManagerBase &PM, std::unique_ptr<MIRParser> &MIR,
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const TargetMachine &TM, StringRef MIRCode, const char *FuncName) {
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SMDiagnostic Diagnostic;
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std::unique_ptr<MemoryBuffer> MBuffer = MemoryBuffer::getMemBuffer(MIRCode);
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MIR = createMIRParser(std::move(MBuffer), Context);
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if (!MIR)
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return nullptr;
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std::unique_ptr<Module> M = MIR->parseIRModule();
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if (!M)
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return nullptr;
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M->setDataLayout(TM.createDataLayout());
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MachineModuleInfo *MMI = new MachineModuleInfo(&TM);
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if (MIR->parseMachineFunctions(*M, *MMI))
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return nullptr;
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PM.add(MMI);
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return M;
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}
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typedef std::function<void(MachineFunction&,LiveIntervals&)> LiveIntervalTest;
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struct TestPass : public MachineFunctionPass {
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static char ID;
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TestPass() : MachineFunctionPass(ID) {
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// We should never call this but always use PM.add(new TestPass(...))
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abort();
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}
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TestPass(LiveIntervalTest T) : MachineFunctionPass(ID), T(T) {
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initializeTestPassPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override {
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LiveIntervals &LIS = getAnalysis<LiveIntervals>();
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T(MF, LIS);
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EXPECT_TRUE(MF.verify(this));
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return true;
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesAll();
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AU.addRequired<LiveIntervals>();
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AU.addPreserved<LiveIntervals>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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private:
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LiveIntervalTest T;
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};
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static MachineInstr &getMI(MachineFunction &MF, unsigned At,
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unsigned BlockNum) {
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MachineBasicBlock &MBB = *MF.getBlockNumbered(BlockNum);
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unsigned I = 0;
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for (MachineInstr &MI : MBB) {
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if (I == At)
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return MI;
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++I;
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}
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llvm_unreachable("Instruction not found");
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}
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/**
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* Move instruction number \p From in front of instruction number \p To and
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* update affected liveness intervals with LiveIntervalAnalysis::handleMove().
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*/
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static void testHandleMove(MachineFunction &MF, LiveIntervals &LIS,
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unsigned From, unsigned To, unsigned BlockNum = 0) {
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MachineInstr &FromInstr = getMI(MF, From, BlockNum);
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MachineInstr &ToInstr = getMI(MF, To, BlockNum);
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MachineBasicBlock &MBB = *FromInstr.getParent();
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MBB.splice(ToInstr.getIterator(), &MBB, FromInstr.getIterator());
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LIS.handleMove(FromInstr, true);
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}
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static void liveIntervalTest(StringRef MIRFunc, LiveIntervalTest T) {
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LLVMContext Context;
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std::unique_ptr<TargetMachine> TM = createTargetMachine();
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// This test is designed for the X86 backend; stop if it is not available.
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if (!TM)
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return;
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legacy::PassManager PM;
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SmallString<160> S;
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StringRef MIRString = (Twine(R"MIR(
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---
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...
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name: func
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registers:
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- { id: 0, class: sreg_64 }
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body: |
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bb.0:
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)MIR") + Twine(MIRFunc) + Twine("...\n")).toNullTerminatedStringRef(S);
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std::unique_ptr<MIRParser> MIR;
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std::unique_ptr<Module> M = parseMIR(Context, PM, MIR, *TM, MIRString,
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"func");
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ASSERT_TRUE(M);
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PM.add(new TestPass(T));
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PM.run(*M);
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}
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} // End of anonymous namespace.
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char TestPass::ID = 0;
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INITIALIZE_PASS(TestPass, "testpass", "testpass", false, false)
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TEST(LiveIntervalTest, MoveUpDef) {
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// Value defined.
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liveIntervalTest(R"MIR(
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S_NOP 0
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S_NOP 0
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early-clobber %0 = IMPLICIT_DEF
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S_NOP 0, implicit %0
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)MIR", [](MachineFunction &MF, LiveIntervals &LIS) {
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testHandleMove(MF, LIS, 2, 1);
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});
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}
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TEST(LiveIntervalTest, MoveUpRedef) {
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liveIntervalTest(R"MIR(
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%0 = IMPLICIT_DEF
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S_NOP 0
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%0 = IMPLICIT_DEF implicit %0(tied-def 0)
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S_NOP 0, implicit %0
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)MIR", [](MachineFunction &MF, LiveIntervals &LIS) {
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testHandleMove(MF, LIS, 2, 1);
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});
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}
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TEST(LiveIntervalTest, MoveUpEarlyDef) {
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liveIntervalTest(R"MIR(
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S_NOP 0
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S_NOP 0
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early-clobber %0 = IMPLICIT_DEF
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S_NOP 0, implicit %0
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)MIR", [](MachineFunction &MF, LiveIntervals &LIS) {
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testHandleMove(MF, LIS, 2, 1);
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});
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}
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TEST(LiveIntervalTest, MoveUpEarlyRedef) {
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liveIntervalTest(R"MIR(
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%0 = IMPLICIT_DEF
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S_NOP 0
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early-clobber %0 = IMPLICIT_DEF implicit %0(tied-def 0)
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S_NOP 0, implicit %0
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)MIR", [](MachineFunction &MF, LiveIntervals &LIS) {
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testHandleMove(MF, LIS, 2, 1);
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});
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}
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TEST(LiveIntervalTest, MoveUpKill) {
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liveIntervalTest(R"MIR(
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%0 = IMPLICIT_DEF
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S_NOP 0
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S_NOP 0, implicit %0
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)MIR", [](MachineFunction &MF, LiveIntervals &LIS) {
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testHandleMove(MF, LIS, 2, 1);
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});
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}
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TEST(LiveIntervalTest, MoveUpKillFollowing) {
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liveIntervalTest(R"MIR(
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%0 = IMPLICIT_DEF
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S_NOP 0
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S_NOP 0, implicit %0
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S_NOP 0, implicit %0
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)MIR", [](MachineFunction &MF, LiveIntervals &LIS) {
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testHandleMove(MF, LIS, 2, 1);
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});
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}
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// TODO: Construct a situation where we have intervals following a hole
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// while still having connected components.
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TEST(LiveIntervalTest, MoveDownDef) {
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// Value defined.
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liveIntervalTest(R"MIR(
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S_NOP 0
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early-clobber %0 = IMPLICIT_DEF
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S_NOP 0
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S_NOP 0, implicit %0
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)MIR", [](MachineFunction &MF, LiveIntervals &LIS) {
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testHandleMove(MF, LIS, 1, 2);
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});
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}
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TEST(LiveIntervalTest, MoveDownRedef) {
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liveIntervalTest(R"MIR(
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%0 = IMPLICIT_DEF
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%0 = IMPLICIT_DEF implicit %0(tied-def 0)
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S_NOP 0
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S_NOP 0, implicit %0
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)MIR", [](MachineFunction &MF, LiveIntervals &LIS) {
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testHandleMove(MF, LIS, 1, 2);
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});
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}
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TEST(LiveIntervalTest, MoveDownEarlyDef) {
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liveIntervalTest(R"MIR(
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S_NOP 0
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early-clobber %0 = IMPLICIT_DEF
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S_NOP 0
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S_NOP 0, implicit %0
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)MIR", [](MachineFunction &MF, LiveIntervals &LIS) {
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testHandleMove(MF, LIS, 1, 2);
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});
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}
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TEST(LiveIntervalTest, MoveDownEarlyRedef) {
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liveIntervalTest(R"MIR(
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%0 = IMPLICIT_DEF
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early-clobber %0 = IMPLICIT_DEF implicit %0(tied-def 0)
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S_NOP 0
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S_NOP 0, implicit %0
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)MIR", [](MachineFunction &MF, LiveIntervals &LIS) {
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testHandleMove(MF, LIS, 1, 2);
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});
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}
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TEST(LiveIntervalTest, MoveDownKill) {
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liveIntervalTest(R"MIR(
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%0 = IMPLICIT_DEF
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S_NOP 0, implicit %0
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S_NOP 0
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)MIR", [](MachineFunction &MF, LiveIntervals &LIS) {
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testHandleMove(MF, LIS, 1, 2);
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});
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}
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TEST(LiveIntervalTest, MoveDownKillFollowing) {
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liveIntervalTest(R"MIR(
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%0 = IMPLICIT_DEF
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S_NOP 0
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S_NOP 0, implicit %0
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S_NOP 0, implicit %0
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)MIR", [](MachineFunction &MF, LiveIntervals &LIS) {
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testHandleMove(MF, LIS, 1, 2);
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});
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}
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TEST(LiveIntervalTest, MoveUndefUse) {
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liveIntervalTest(R"MIR(
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%0 = IMPLICIT_DEF
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S_NOP 0, implicit undef %0
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S_NOP 0, implicit %0
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S_NOP 0
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)MIR", [](MachineFunction &MF, LiveIntervals &LIS) {
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testHandleMove(MF, LIS, 1, 3);
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});
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}
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TEST(LiveIntervalTest, MoveUpValNos) {
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// handleMoveUp() had a bug where it would reuse the value number of the
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// destination segment, even though we have no guarntee that this valno wasn't
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// used in other segments.
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liveIntervalTest(R"MIR(
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successors: %bb.1, %bb.2
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%0 = IMPLICIT_DEF
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S_CBRANCH_VCCNZ %bb.2, implicit undef %vcc
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S_BRANCH %bb.1
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bb.2:
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S_NOP 0, implicit %0
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bb.1:
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successors: %bb.2
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%0 = IMPLICIT_DEF implicit %0(tied-def 0)
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%0 = IMPLICIT_DEF implicit %0(tied-def 0)
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%0 = IMPLICIT_DEF implicit %0(tied-def 0)
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S_BRANCH %bb.2
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)MIR", [](MachineFunction &MF, LiveIntervals &LIS) {
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testHandleMove(MF, LIS, 2, 0, 2);
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});
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}
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TEST(LiveIntervalTest, MoveOverUndefUse0) {
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// findLastUseBefore() used by handleMoveUp() must ignore undef operands.
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liveIntervalTest(R"MIR(
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%0 = IMPLICIT_DEF
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S_NOP 0
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S_NOP 0, implicit undef %0
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%0 = IMPLICIT_DEF implicit %0(tied-def 0)
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)MIR", [](MachineFunction &MF, LiveIntervals &LIS) {
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testHandleMove(MF, LIS, 3, 1);
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});
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}
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TEST(LiveIntervalTest, MoveOverUndefUse1) {
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// findLastUseBefore() used by handleMoveUp() must ignore undef operands.
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liveIntervalTest(R"MIR(
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%sgpr0 = IMPLICIT_DEF
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S_NOP 0
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S_NOP 0, implicit undef %sgpr0
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%sgpr0 = IMPLICIT_DEF implicit %sgpr0(tied-def 0)
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)MIR", [](MachineFunction &MF, LiveIntervals &LIS) {
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testHandleMove(MF, LIS, 3, 1);
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});
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}
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TEST(LiveIntervalTest, SubRegMoveDown) {
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// Subregister ranges can have holes inside a basic block. Check for a
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// movement of the form 32->150 in a liverange [16, 32) [100,200).
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liveIntervalTest(R"MIR(
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successors: %bb.1, %bb.2
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%0 = IMPLICIT_DEF
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S_CBRANCH_VCCNZ %bb.2, implicit undef %vcc
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S_BRANCH %bb.1
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bb.2:
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successors: %bb.1
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S_NOP 0, implicit %0.sub0
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S_NOP 0, implicit %0.sub1
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S_NOP 0
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undef %0.sub0 = IMPLICIT_DEF
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%0.sub1 = IMPLICIT_DEF
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bb.1:
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S_NOP 0, implicit %0
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)MIR", [](MachineFunction &MF, LiveIntervals &LIS) {
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// Scheduler behaviour: Clear def,read-undef flag and move.
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MachineInstr &MI = getMI(MF, 3, /*BlockNum=*/1);
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MI.getOperand(0).setIsUndef(false);
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testHandleMove(MF, LIS, 1, 4, /*BlockNum=*/1);
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});
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}
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TEST(LiveIntervalTest, SubRegMoveUp) {
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// handleMoveUp had a bug not updating valno of segment incoming to bb.2
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// after swapping subreg definitions.
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liveIntervalTest(R"MIR(
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successors: %bb.1, %bb.2
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undef %0.sub0 = IMPLICIT_DEF
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%0.sub1 = IMPLICIT_DEF
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S_CBRANCH_VCCNZ %bb.2, implicit undef %vcc
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S_BRANCH %bb.1
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bb.1:
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S_NOP 0, implicit %0.sub1
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bb.2:
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S_NOP 0, implicit %0.sub1
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)MIR", [](MachineFunction &MF, LiveIntervals &LIS) {
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testHandleMove(MF, LIS, 1, 0);
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});
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}
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int main(int argc, char **argv) {
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::testing::InitGoogleTest(&argc, argv);
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initLLVM();
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return RUN_ALL_TESTS();
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}
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