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AsmParser
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[AMDGPU] Assembler: Change dpp_ctrl syntax to match sp3
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2016-03-18 15:35:51 +00:00 |
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Disassembler
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[AMDGPU] Disassembler: support for DPP
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2016-03-31 14:15:04 +00:00 |
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InstPrinter
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[AMDGPU] Assembler: Change dpp_ctrl syntax to match sp3
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2016-03-18 15:35:51 +00:00 |
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MCTargetDesc
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AMDGPU: R600 code splitting cleanup
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2016-03-11 08:00:27 +00:00 |
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TargetInfo
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Remove autoconf support
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2016-01-26 21:29:08 +00:00 |
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Utils
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fix sanitizer-ppc64be-linux failure for r262804
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2016-03-06 15:13:54 +00:00 |
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AMDGPU.h
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AMDGPU: Add SIWholeQuadMode pass
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2016-03-21 20:28:33 +00:00 |
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AMDGPU.td
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AMDGPU: More bits of frame index are known to be zero
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2016-02-27 20:26:57 +00:00 |
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AMDGPUAlwaysInlinePass.cpp
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AMDGPU: Minor cleanups to always inline pass
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2015-07-13 19:08:36 +00:00 |
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AMDGPUAnnotateKernelFeatures.cpp
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AMDGPU: Stop checking intrinsics not used by HSA for dispatch-ptr
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2016-01-30 05:10:59 +00:00 |
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AMDGPUAnnotateUniformValues.cpp
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AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions
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2016-02-12 23:45:29 +00:00 |
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AMDGPUAsmPrinter.cpp
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Silencing warnings from MSVC 2015 Update 2. All of these changes silence "C4334 '<<': result of 32-bit shift implicitly converted to 64 bits (was 64-bit shift intended?)". NFC.
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2016-03-30 21:30:00 +00:00 |
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AMDGPUAsmPrinter.h
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AMDGPU: R600 code splitting cleanup
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2016-03-11 08:00:27 +00:00 |
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AMDGPUCallingConv.td
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AMDGPU/SI: Add support for non-void functions
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2016-01-13 17:23:04 +00:00 |
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AMDGPUFrameLowering.cpp
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AMDGPU: Fix old comments that mention AMDIL
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2016-01-20 21:22:21 +00:00 |
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AMDGPUFrameLowering.h
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AMDGPU: Create emergency stack slots during frame lowering
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2015-11-06 18:17:45 +00:00 |
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AMDGPUISelDAGToDAG.cpp
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Fix sequence point warning. NFC.
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2016-03-24 10:53:28 +00:00 |
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AMDGPUISelLowering.cpp
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Silencing warnings from MSVC 2015 Update 2. All of these changes silence "C4334 '<<': result of 32-bit shift implicitly converted to 64 bits (was 64-bit shift intended?)". NFC.
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2016-03-30 21:30:00 +00:00 |
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AMDGPUISelLowering.h
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AMDGPU: R600 code splitting cleanup
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2016-03-11 08:00:27 +00:00 |
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AMDGPUInstrInfo.cpp
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AMDGPU: Move subtarget specific code out of AMDGPUInstrInfo.cpp
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2016-01-28 16:04:37 +00:00 |
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AMDGPUInstrInfo.h
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AMDGPU: Add SIWholeQuadMode pass
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2016-03-21 20:28:33 +00:00 |
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AMDGPUInstrInfo.td
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AMDGPU: Rename intrinsic to better match instruction name
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2016-02-13 01:03:00 +00:00 |
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AMDGPUInstructions.td
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AMDGPU: Match more med3 integer patterns
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2016-03-07 21:54:48 +00:00 |
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AMDGPUIntrinsicInfo.cpp
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[llvm-tblgen] Avoid StringMatcher for GCC and MS builtin names
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2016-01-27 01:43:12 +00:00 |
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AMDGPUIntrinsicInfo.h
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AMDGPU: R600 code splitting cleanup
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2016-03-11 08:00:27 +00:00 |
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AMDGPUIntrinsics.td
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AMDGPU: Remove bfi and bfm intrinsics
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2016-02-08 19:06:01 +00:00 |
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AMDGPUMCInstLower.cpp
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AMDGPU: Verify instructions in non-debug builds as well
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2016-03-16 09:10:42 +00:00 |
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AMDGPUMCInstLower.h
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AMDGPU: R600 code splitting cleanup
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2016-03-11 08:00:27 +00:00 |
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AMDGPUMachineFunction.cpp
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AMDGPU/SI: Add getShaderType() function to Utils/
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2015-12-15 16:26:16 +00:00 |
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AMDGPUMachineFunction.h
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AMDGPU: R600 code splitting cleanup
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2016-03-11 08:00:27 +00:00 |
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AMDGPUOpenCLImageTypeLoweringPass.cpp
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AMDGPU/SI: Remove assert from AMDGPUOpenCLImageTypeLowering pass
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2015-10-01 21:16:05 +00:00 |
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AMDGPUPromoteAlloca.cpp
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AMDGPU: Promote alloca should skip volatiles
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2016-03-23 23:17:29 +00:00 |
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AMDGPURegisterInfo.cpp
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…
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AMDGPURegisterInfo.h
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AMDGPU: R600 code splitting cleanup
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2016-03-11 08:00:27 +00:00 |
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AMDGPURegisterInfo.td
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AMDGPU: Set SubRegIndex size and offset
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2015-07-30 17:03:11 +00:00 |
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AMDGPUSubtarget.cpp
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AMDGPU/SI: Enable lanemask tracking in misched
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2016-03-30 16:35:09 +00:00 |
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AMDGPUSubtarget.h
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AMDGPU: More bits of frame index are known to be zero
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2016-02-27 20:26:57 +00:00 |
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AMDGPUTargetMachine.cpp
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AMDGPU: Add SIWholeQuadMode pass
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2016-03-21 20:28:33 +00:00 |
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AMDGPUTargetMachine.h
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AMDGPU: R600 code splitting cleanup
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2016-03-11 08:00:27 +00:00 |
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AMDGPUTargetObjectFile.cpp
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AMDGPU/SI: Emit constant variables in the .hsatext section when targeting HSA
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2015-12-15 22:39:36 +00:00 |
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AMDGPUTargetObjectFile.h
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AMDGPU/SI: Emit constant arrays in the .text section
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2015-12-10 02:13:01 +00:00 |
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AMDGPUTargetTransformInfo.cpp
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AMDGPU: Cost model for basic integer operations
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2016-03-25 01:16:40 +00:00 |
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AMDGPUTargetTransformInfo.h
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AMDGPU: Partially implement getArithmeticInstrCost for FP ops
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2016-03-25 01:00:32 +00:00 |
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AMDILCFGStructurizer.cpp
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Bug 20810: Use report_fatal_error instead of unreachable
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2016-03-02 03:33:55 +00:00 |
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AMDKernelCodeT.h
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[AMDGPU] fix amd_kernel_code_t bit field position as per spec (added missing reserved fields)
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2016-02-24 10:54:25 +00:00 |
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CIInstructions.td
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[AMDGPU] Disassembler: Added basic disassembler for AMDGPU target
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2016-02-18 03:42:32 +00:00 |
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CMakeLists.txt
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AMDGPU: Add SIWholeQuadMode pass
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2016-03-21 20:28:33 +00:00 |
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CaymanInstructions.td
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AMDGPU: Remove 24-bit intrinsics
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2016-01-29 10:05:16 +00:00 |
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EvergreenInstructions.td
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AMDGPU: Remove 24-bit intrinsics
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2016-01-29 10:05:16 +00:00 |
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LLVMBuild.txt
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[AMDGPU] Disassembler: Added basic disassembler for AMDGPU target
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2016-02-18 03:42:32 +00:00 |
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Processors.td
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AMDGPU/SI: Add Polaris support
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2016-03-24 15:31:05 +00:00 |
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R600ClauseMergePass.cpp
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…
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R600ControlFlowFinalizer.cpp
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AMDGPU: Fix a use-after free and a missing break
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2016-03-25 18:33:16 +00:00 |
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R600Defines.h
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AMDGPU: R600 code splitting cleanup
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2016-03-11 08:00:27 +00:00 |
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R600EmitClauseMarkers.cpp
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…
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R600ExpandSpecialInstrs.cpp
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…
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R600ISelLowering.cpp
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[DAG] use isUndef() ; NFCI
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2016-03-14 17:28:46 +00:00 |
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R600ISelLowering.h
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AMDGPU: R600 code splitting cleanup
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2016-03-11 08:00:27 +00:00 |
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R600InstrFormats.td
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…
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R600InstrInfo.cpp
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AMDGPU: Simplify boolean conditional return statements
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2016-03-02 23:00:21 +00:00 |
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R600InstrInfo.h
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AMDGPU: R600 code splitting cleanup
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2016-03-11 08:00:27 +00:00 |
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R600Instructions.td
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AMDGPU: Rename intrinsic to better match instruction name
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2016-02-13 01:03:00 +00:00 |
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R600Intrinsics.td
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AMDGPU: Move AMDGPU intrinsics only used by R600
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2016-01-26 04:49:24 +00:00 |
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R600MachineFunctionInfo.cpp
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…
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R600MachineFunctionInfo.h
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AMDGPU: R600 code splitting cleanup
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2016-03-11 08:00:27 +00:00 |
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R600MachineScheduler.cpp
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…
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R600MachineScheduler.h
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AMDGPU: R600 code splitting cleanup
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2016-03-11 08:00:27 +00:00 |
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R600OptimizeVectorRegisters.cpp
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AMDGPU: Remove implicit ilist iterator conversions, NFC
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2015-10-13 20:07:10 +00:00 |
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R600Packetizer.cpp
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AMDGPU: Simplify boolean conditional return statements
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2016-03-02 23:00:21 +00:00 |
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R600RegisterInfo.cpp
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…
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R600RegisterInfo.h
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AMDGPU: R600 code splitting cleanup
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2016-03-11 08:00:27 +00:00 |
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R600RegisterInfo.td
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…
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R600Schedule.td
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…
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R600TextureIntrinsicsReplacer.cpp
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AMDGPU: Rename some r600 intrinsics to use correct TargetPrefix
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2016-01-22 19:00:09 +00:00 |
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R700Instructions.td
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…
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SIAnnotateControlFlow.cpp
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AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions
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2016-02-12 23:45:29 +00:00 |
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SIDefines.h
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AMDGPU: R600 code splitting cleanup
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2016-03-11 08:00:27 +00:00 |
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SIFixControlFlowLiveIntervals.cpp
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AMDGPU: Remove unused includes
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2015-09-25 00:28:43 +00:00 |
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SIFixSGPRCopies.cpp
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AMDGPU/SI: Fold operands with sub-registers
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2016-01-07 17:10:29 +00:00 |
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SIFixSGPRLiveRanges.cpp
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AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions
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2016-02-12 23:45:29 +00:00 |
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SIFoldOperands.cpp
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AMDGPU: Fix passes depending on dominator tree for no reason
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2016-02-11 06:15:34 +00:00 |
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SIFrameLowering.cpp
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AMDGPU/SI: Don't try to move scratch wave offset when there are no free SGPRs
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2016-03-03 03:45:09 +00:00 |
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SIFrameLowering.h
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AMDGPU: Remove SIPrepareScratchRegs
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2015-11-30 21:15:53 +00:00 |
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SIISelLowering.cpp
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AMDGPU/SI: Implement GroupStaticSize Intrinsic for Dynamic LDS
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2016-03-15 17:28:44 +00:00 |
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SIISelLowering.h
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AMDGPU: R600 code splitting cleanup
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2016-03-11 08:00:27 +00:00 |
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SIInsertNopsPass.cpp
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AMDGPU: Insert two S_NOP instructions for every high level source statement.
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2016-03-03 03:53:29 +00:00 |
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SIInsertWaits.cpp
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AMDGPU/SI: Handle wait states required for DPP instructions
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2016-03-14 17:05:56 +00:00 |
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SIInstrFormats.td
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[AMDGPU] fix MADAK/MADMK instructions operand namings to match encoding fields.
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2016-04-01 13:13:12 +00:00 |
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SIInstrInfo.cpp
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AMDGPU/SI: Limit load clustering to 16 bytes instead of 4 instructions
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2016-03-28 16:10:13 +00:00 |
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SIInstrInfo.h
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AMDGPU: Add SIWholeQuadMode pass
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2016-03-21 20:28:33 +00:00 |
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SIInstrInfo.td
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[AMDGPU] fix MADAK/MADMK instructions operand namings to match encoding fields.
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2016-04-01 13:13:12 +00:00 |
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SIInstructions.td
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AMDGPU: Add frexp_exp intrinsic
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2016-03-30 22:28:52 +00:00 |
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SIIntrinsics.td
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AMDGPU: Remove old sample intrinsics
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2016-01-26 04:38:08 +00:00 |
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SILoadStoreOptimizer.cpp
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Test commit access
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2016-03-29 15:15:44 +00:00 |
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SILowerControlFlow.cpp
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AMDGPU: Add SIWholeQuadMode pass
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2016-03-21 20:28:33 +00:00 |
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SILowerI1Copies.cpp
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AMDGPU: Fix passes depending on dominator tree for no reason
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2016-02-11 06:15:34 +00:00 |
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SIMachineFunctionInfo.cpp
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AMDGPU/SI: Add support for spiling SGPRs to scratch buffer
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2016-03-04 18:31:18 +00:00 |
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SIMachineFunctionInfo.h
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AMDGPU: R600 code splitting cleanup
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2016-03-11 08:00:27 +00:00 |
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SIMachineScheduler.cpp
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[TII] Allow getMemOpBaseRegImmOfs() to accept negative offsets. NFC.
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2016-03-09 16:00:35 +00:00 |
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SIMachineScheduler.h
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AMDGPU: R600 code splitting cleanup
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2016-03-11 08:00:27 +00:00 |
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SIRegisterInfo.cpp
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AMDGPU: Cache information about register pressure sets
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2016-03-23 01:53:22 +00:00 |
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SIRegisterInfo.h
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AMDGPU: Cache information about register pressure sets
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2016-03-23 01:53:22 +00:00 |
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SIRegisterInfo.td
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AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions
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2016-02-12 23:45:29 +00:00 |
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SISchedule.td
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AMDGPU/SI: Improve MachineSchedModel definition
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2016-03-30 16:35:13 +00:00 |
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SIShrinkInstructions.cpp
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AMDGPU: Materialize sign bits with bfrev
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2016-03-11 07:42:49 +00:00 |
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SITypeRewriter.cpp
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AMDGPU/SI: Fix crash when inline assembly is used in a graphics shader
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2016-01-06 22:01:04 +00:00 |
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SIWholeQuadMode.cpp
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AMDGPU: Fix dangling references introduced by r263982
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2016-03-21 22:54:02 +00:00 |
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VIInstrFormats.td
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[AMDGPU] Fix SMEM instructions encoding/operand namings
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2016-03-10 13:06:08 +00:00 |
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VIInstructions.td
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[AMDGPU] Assembler: change v_madmk operands to have same order as mad.
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2016-03-11 09:27:25 +00:00 |
5b3559c1ec