forked from OSchip/llvm-project
52 lines
1.2 KiB
Plaintext
52 lines
1.2 KiB
Plaintext
{
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"arrays" : [
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{
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"name" : "MemRef_B",
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"sizes" : [ "*", "1024" ]
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},
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{
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"name" : "MemRef_A",
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"sizes" : [ "*", "1056" ],
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"type" : "double"
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},
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{
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"name" : "D",
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"sizes" : [ "270336" ],
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"type" : "double"
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},
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{
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"name" : "E",
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"sizes" : [ "270336", "200000" ],
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"type" : "double"
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},
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{
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"name" : "F",
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"sizes" : [ "270336" ],
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"type" : "i64"
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}
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],
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"context" : "{ : }",
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"name" : "%bb9---%bb26",
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"statements" : [
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{
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"accesses" : [
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{
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"kind" : "read",
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"relation" : "{ Stmt_bb12[i0, i1, i2] -> E[i2, i0] }"
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},
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{
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"kind" : "read",
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"relation" : "{ Stmt_bb12[i0, i1, i2] -> MemRef_beta[] }"
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},
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{
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"kind" : "write",
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"relation" : "{ Stmt_bb12[i0, i1, i2] -> MemRef_A[i0, i1] }"
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}
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],
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"domain" : "{ Stmt_bb12[i0, i1, i2] : 0 <= i0 <= 1055 and 0 <= i1 <= 1055 and 0 <= i2 <= 1023 }",
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"name" : "Stmt_bb12",
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"schedule" : "{ Stmt_bb12[i0, i1, i2] -> [i0, i1, i2] }"
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}
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]
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}
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