forked from OSchip/llvm-project
54 lines
1.9 KiB
LLVM
54 lines
1.9 KiB
LLVM
; RUN: llc < %s -march=x86 -mcpu=core2 | FileCheck %s
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; RUN: llc < %s -march=x86-64 -mcpu=corei7 | FileCheck %s
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; Verify that the backend correctly combines SSE2 builtin intrinsics.
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define <4 x i32> @test_psra_1(<4 x i32> %A) {
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%1 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %A, i32 3)
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%2 = tail call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %1, <4 x i32> <i32 3, i32 0, i32 7, i32 0>)
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%3 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %2, i32 2)
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ret <4 x i32> %3
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}
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; CHECK-LABEL: test_psra_1
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; CHECK: psrad $8, %xmm0
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; CHECK-NEXT: ret
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define <8 x i16> @test_psra_2(<8 x i16> %A) {
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%1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %A, i32 3)
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%2 = tail call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %1, <8 x i16> <i16 3, i16 0, i16 0, i16 0, i16 7, i16 0, i16 0, i16 0>)
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%3 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %2, i32 2)
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ret <8 x i16> %3
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}
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; CHECK-LABEL: test_psra_2
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; CHECK: psraw $8, %xmm0
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; CHECK-NEXT: ret
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define <4 x i32> @test_psra_3(<4 x i32> %A) {
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%1 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %A, i32 0)
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%2 = tail call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %1, <4 x i32> <i32 0, i32 0, i32 7, i32 0>)
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%3 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %2, i32 0)
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ret <4 x i32> %3
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}
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; CHECK-LABEL: test_psra_3
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; CHECK-NOT: psrad
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; CHECK: ret
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define <8 x i16> @test_psra_4(<8 x i16> %A) {
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%1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %A, i32 0)
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%2 = tail call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %1, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 7, i16 0, i16 0, i16 0>)
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%3 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %2, i32 0)
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ret <8 x i16> %3
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}
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; CHECK-LABEL: test_psra_4
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; CHECK-NOT: psraw
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; CHECK: ret
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declare <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16>, <8 x i16>)
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declare <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16>, i32)
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declare <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32>, <4 x i32>)
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declare <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32>, i32)
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