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llvm-project/llvm/lib/Target/RISCV
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Roger Ferrer Ibanez c8f4dbbc63 [RISCV] Fix incorrect use of MCInstBuilder 
This is a fix for r339314.

MCInstBuilder uses the named parameter idiom and an 'operator MCInst&' to ease
the creation of MCInsts. As the object of MCInstBuilder owns the MCInst is
manipulating, the lifetime of the MCInst is bound to that of MCInstBuilder.

In r339314 I bound a reference to the MCInst in an initializer. The
temporary of MCInstBuilder (and also its MCInst) is destroyed at the end of
the declaration leading to a dangling reference.

Fix this by using MCInstBuilder inside an argument of a function call.
Temporaries in function calls are destroyed in the enclosing full expression,
so the the reference to MCInst is still valid when emitToStreamer executes.

llvm-svn: 339654
 		2018-08-14 08:30:42 +00:00
..
AsmParser [RISCV] Fix incorrect use of MCInstBuilder 2018-08-14 08:30:42 +00:00
Disassembler Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
InstPrinter [RISCV] Tablegen-driven Instruction Compression. 2018-04-06 21:07:05 +00:00
MCTargetDesc Test commit: fix punctuation 2018-08-14 08:08:39 +00:00
TargetInfo
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CMakeLists.txt [RISCV] Add machine function pass to merge base + offset 2018-06-27 20:51:42 +00:00
LLVMBuild.txt
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RISCV.h [RISCV] Add machine function pass to merge base + offset 2018-06-27 20:51:42 +00:00
RISCV.td [RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxation 2018-05-15 01:28:50 +00:00
RISCVAsmPrinter.cpp Revert "[RISCV] implement li pseudo instruction" 2018-04-18 19:02:31 +00:00
RISCVCallingConv.td [RISCV] Add support for _interrupt attribute 2018-07-26 17:49:43 +00:00
RISCVFrameLowering.cpp [RISCV] Add support for _interrupt attribute 2018-07-26 17:49:43 +00:00
RISCVFrameLowering.h
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RISCVISelDAGToDAG.cpp [RISCV] Add machine function pass to merge base + offset 2018-06-27 20:51:42 +00:00
RISCVISelLowering.cpp [RISCV] Add support for _interrupt attribute 2018-07-26 17:49:43 +00:00
RISCVISelLowering.h [RISCV] Add support for _interrupt attribute 2018-07-26 17:49:43 +00:00
RISCVInstrFormats.td [RISCV] AsmParser support for the li pseudo instruction 2018-06-07 15:35:47 +00:00
RISCVInstrFormatsC.td
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RISCVInstrInfo.cpp [RISCV] Add support for _interrupt attribute 2018-07-26 17:49:43 +00:00
RISCVInstrInfo.h [RISCV] Implement isLoadFromStackSlot and isStoreToStackSlot 2018-04-26 15:34:27 +00:00
RISCVInstrInfo.td [RISCV] Add "lla" pseudo-instruction to assembler 2018-08-09 07:08:20 +00:00
RISCVInstrInfoA.td [RISCV] Add codegen support for atomic load/stores with RV32A 2018-06-13 12:04:51 +00:00
RISCVInstrInfoC.td [RISC-V] Fixed alias for addi x2, x2, 0 2018-08-09 20:51:53 +00:00
RISCVInstrInfoD.td [RISCV] Add InstAlias definitions for fgt.{s|d}, fge.{s|d} 2018-06-20 14:03:02 +00:00
RISCVInstrInfoF.td [RISCV] Accept fmv.s.x and fmv.x.s as mnemonic aliases for fmv.w.x and fmv.x.w 2018-06-20 18:42:25 +00:00
RISCVInstrInfoM.td
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RISCVMCInstLower.cpp
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RISCVMachineFunctionInfo.h [RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling conv 2018-04-12 05:34:25 +00:00
RISCVMergeBaseOffset.cpp Test commit. 2018-08-02 05:38:18 +00:00
RISCVRegisterInfo.cpp [RISCV] Add support for _interrupt attribute 2018-07-26 17:49:43 +00:00
RISCVRegisterInfo.h [RISCV] Set isReMaterializable on ADDI and LUI instructions 2018-05-17 15:51:37 +00:00
RISCVRegisterInfo.td [RISCV] Lower the tail pseudoinstruction 2018-05-23 22:44:08 +00:00
RISCVSubtarget.cpp
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RISCVSubtarget.h [RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxation 2018-05-15 01:28:50 +00:00
RISCVTargetMachine.cpp [RISCV] Add machine function pass to merge base + offset 2018-06-27 20:51:42 +00:00
RISCVTargetMachine.h
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RISCVTargetObjectFile.cpp
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RISCVTargetObjectFile.h
…