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Kang Zhang b083d7a346 [PowerPC] Fix the unexpected modification caused by D62993 in LowerSELECT_CC for power9 
Summary:
The patch D62993 : `[PowerPC] Emit scalar min/max instructions with unsafe fp math`
has modified the functionality when `Subtarget.hasP9Vector() && (!HasNoInfs || !HasNoNaNs)`,
 this modification is not expected.

Reviewed By: nemanjai

Differential Revision: https://reviews.llvm.org/D74701
 		2020-02-26 02:59:03 +00:00
..
AArch64 [Codegen] Revert rL354676/rL354677 and followups - introduced PR43446 miscompile 2020-02-25 20:30:12 +03:00
AMDGPU AMDGPU/GlobalISel: Un-XFAIL a test 2020-02-25 16:46:46 +00:00
ARC
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ARM Don't generate libcalls for wide shift on Windows ARM (PR42711) 2020-02-25 11:54:07 +01:00
AVR
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BPF Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
Generic Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
Hexagon [Hexagon] Lower vector predicate store 2020-02-24 15:43:04 -06:00
Inputs
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Lanai Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
MIR [MIR][ARM] MachineOperand comments 2020-02-24 14:19:21 +00:00
MSP430
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Mips [MIPS GlobalISel] Legalize non-power-of-2 and unaligned load and store 2020-02-19 12:02:27 +01:00
NVPTX [NVPTX, LSV] Move the LSV optimization pass to later when the graph is cleaner 2020-02-13 12:15:38 -08:00
PowerPC [PowerPC] Fix the unexpected modification caused by D62993 in LowerSELECT_CC for power9 2020-02-26 02:59:03 +00:00
RISCV [RISCV] Implement mayBeEmittedAsTailCall for tail call optimization 2020-02-18 23:56:42 +08:00
SPARC Emit register names in cfi assembly directives 2020-02-25 14:00:01 -05:00
SystemZ [LegalizeTypes] Scalarize non-byte sized loads in WidenRecRes_Load and SplitVecResLoad 2020-02-24 15:14:33 -08:00
Thumb [MIR][ARM] MachineOperand comments 2020-02-24 14:19:21 +00:00
Thumb2 [MIR][ARM] MachineOperand comments 2020-02-24 14:19:21 +00:00
VE [VE] TLS codegen 2020-02-18 16:09:12 +01:00
WebAssembly [WebAssembly] Simplify extract_vector lowering 2020-02-25 13:54:48 -08:00
WinCFGuard
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WinEH
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X86 [SelectionDAG][PowerPC][AArch64][X86][ARM] Add chain input and output the ISD::FLT_ROUNDS_ 2020-02-25 16:58:23 -08:00
XCore [XCore] Add instruction pattern for bitrev 2020-02-21 09:28:49 +08:00