forked from OSchip/llvm-project
71 lines
2.3 KiB
C++
71 lines
2.3 KiB
C++
//===- X86InstructionSelector --------------------------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file declares the targeting of the InstructionSelector class for X86.
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//===----------------------------------------------------------------------===//
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#ifdef LLVM_BUILD_GLOBAL_ISEL
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#ifndef LLVM_LIB_TARGET_X86_X86INSTRUCTIONSELECTOR_H
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#define LLVM_LIB_TARGET_X86_X86INSTRUCTIONSELECTOR_H
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/CodeGen/MachineOperand.h"
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namespace llvm {
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class X86InstrInfo;
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class X86RegisterBankInfo;
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class X86RegisterInfo;
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class X86Subtarget;
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class X86TargetMachine;
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class LLT;
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class RegisterBank;
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class MachineRegisterInfo;
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class MachineFunction;
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class X86InstructionSelector : public InstructionSelector {
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public:
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X86InstructionSelector(const X86Subtarget &STI,
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const X86RegisterBankInfo &RBI);
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bool select(MachineInstr &I) const override;
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private:
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/// tblgen-erated 'select' implementation, used as the initial selector for
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/// the patterns that don't require complex C++.
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bool selectImpl(MachineInstr &I) const;
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// TODO: remove after selectImpl support pattern with a predicate.
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unsigned getFAddOp(LLT &Ty, const RegisterBank &RB) const;
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unsigned getFSubOp(LLT &Ty, const RegisterBank &RB) const;
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unsigned getAddOp(LLT &Ty, const RegisterBank &RB) const;
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unsigned getSubOp(LLT &Ty, const RegisterBank &RB) const;
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unsigned getLoadStoreOp(LLT &Ty, const RegisterBank &RB, unsigned Opc,
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uint64_t Alignment) const;
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bool selectBinaryOp(MachineInstr &I, MachineRegisterInfo &MRI,
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MachineFunction &MF) const;
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bool selectLoadStoreOp(MachineInstr &I, MachineRegisterInfo &MRI,
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MachineFunction &MF) const;
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const X86Subtarget &STI;
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const X86InstrInfo &TII;
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const X86RegisterInfo &TRI;
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const X86RegisterBankInfo &RBI;
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#define GET_GLOBALISEL_TEMPORARIES_DECL
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#include "X86GenGlobalISel.inc"
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#undef GET_GLOBALISEL_TEMPORARIES_DECL
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_X86_X86INSTRUCTIONSELECTOR_H
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#endif // LLVM_BUILD_GLOBAL_ISEL
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