forked from OSchip/llvm-project
127 lines
4.6 KiB
LLVM
127 lines
4.6 KiB
LLVM
; RUN: opt < %s -loop-unroll -unroll-runtime=true -unroll-runtime-epilog=false -unroll-runtime-multi-exit=true -unroll-count=4 -verify-dom-info -S | FileCheck %s
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; REQUIRES: asserts
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; The tests below are for verifying dom tree after runtime unrolling
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; with multiple exit/exiting blocks.
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; We explicitly set the unroll count so that expensiveTripCount computation is allowed.
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; mergedexit block has edges from loop exit blocks.
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define i64 @test1() {
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; CHECK-LABEL: test1(
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; CHECK-LABEL: headerexit:
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; CHECK-NEXT: %addphi = phi i64 [ %add.iv, %header ], [ %add.iv.1, %header.1 ], [ %add.iv.2, %header.2 ], [ %add.iv.3, %header.3 ]
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; CHECK-NEXT: br label %mergedexit
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; CHECK-LABEL: latchexit:
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; CHECK-NEXT: %shftphi = phi i64 [ %shft, %latch ], [ %shft.1, %latch.1 ], [ %shft.2, %latch.2 ], [ %shft.3, %latch.3 ]
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; CHECK-NEXT: br label %mergedexit
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; CHECK-LABEL: mergedexit:
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; CHECK-NEXT: %retval = phi i64 [ %addphi, %headerexit ], [ %shftphi, %latchexit ]
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; CHECK-NEXT: ret i64 %retval
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entry:
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br label %preheader
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preheader: ; preds = %bb
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%trip = zext i32 undef to i64
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br label %header
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header: ; preds = %latch, %preheader
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%iv = phi i64 [ 2, %preheader ], [ %add.iv, %latch ]
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%add.iv = add nuw nsw i64 %iv, 2
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%cmp1 = icmp ult i64 %add.iv, %trip
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br i1 %cmp1, label %latch, label %headerexit
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latch: ; preds = %header
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%shft = ashr i64 %add.iv, 1
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%cmp2 = icmp ult i64 %shft, %trip
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br i1 %cmp2, label %header, label %latchexit
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headerexit: ; preds = %header
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%addphi = phi i64 [ %add.iv, %header ]
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br label %mergedexit
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latchexit: ; preds = %latch
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%shftphi = phi i64 [ %shft, %latch ]
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br label %mergedexit
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mergedexit: ; preds = %latchexit, %headerexit
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%retval = phi i64 [ %addphi, %headerexit ], [ %shftphi, %latchexit ]
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ret i64 %retval
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}
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; mergedexit has edges from loop exit blocks and a block outside the loop.
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define void @test2(i1 %cond, i32 %n) {
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; CHECK-LABEL: header.1:
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; CHECK-NEXT: %add.iv.1 = add nuw nsw i64 %add.iv, 2
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; CHECK: br i1 %cmp1.1, label %latch.1, label %headerexit
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; CHECK-LABEL: latch.3:
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; CHECK: %cmp2.3 = icmp ult i64 %shft.3, %trip
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; CHECK-NEXT: br i1 %cmp2.3, label %header, label %latchexit, !llvm.loop
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entry:
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br i1 %cond, label %preheader, label %mergedexit
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preheader: ; preds = %entry
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%trip = zext i32 %n to i64
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br label %header
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header: ; preds = %latch, %preheader
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%iv = phi i64 [ 2, %preheader ], [ %add.iv, %latch ]
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%add.iv = add nuw nsw i64 %iv, 2
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%cmp1 = icmp ult i64 %add.iv, %trip
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br i1 %cmp1, label %latch, label %headerexit
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latch: ; preds = %header
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%shft = ashr i64 %add.iv, 1
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%cmp2 = icmp ult i64 %shft, %trip
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br i1 %cmp2, label %header, label %latchexit
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headerexit: ; preds = %header
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br label %mergedexit
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latchexit: ; preds = %latch
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br label %mergedexit
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mergedexit: ; preds = %latchexit, %headerexit, %entry
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ret void
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}
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; exitsucc is from loop exit block only.
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define i64 @test3(i32 %n) {
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; CHECK-LABEL: test3(
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; CHECK-LABEL: headerexit:
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; CHECK-NEXT: br label %exitsucc
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; CHECK-LABEL: latchexit:
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; CHECK-NEXT: %shftphi = phi i64 [ %shft, %latch ], [ %shft.1, %latch.1 ], [ %shft.2, %latch.2 ], [ %shft.3, %latch.3 ]
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; CHECK-NEXT: ret i64 %shftphi
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; CHECK-LABEL: exitsucc:
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; CHECK-NEXT: ret i64 96
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entry:
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br label %preheader
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preheader: ; preds = %bb
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%trip = zext i32 %n to i64
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br label %header
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header: ; preds = %latch, %preheader
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%iv = phi i64 [ 2, %preheader ], [ %add.iv, %latch ]
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%add.iv = add nuw nsw i64 %iv, 2
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%cmp1 = icmp ult i64 %add.iv, %trip
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br i1 %cmp1, label %latch, label %headerexit
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latch: ; preds = %header
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%shft = ashr i64 %add.iv, 1
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%cmp2 = icmp ult i64 %shft, %trip
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br i1 %cmp2, label %header, label %latchexit
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headerexit: ; preds = %header
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br label %exitsucc
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latchexit: ; preds = %latch
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%shftphi = phi i64 [ %shft, %latch ]
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ret i64 %shftphi
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exitsucc: ; preds = %headerexit
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ret i64 96
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}
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