forked from OSchip/llvm-project
118 lines
3.5 KiB
LLVM
118 lines
3.5 KiB
LLVM
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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@glob = common local_unnamed_addr global i16 0, align 2
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @test_igtss(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: test_igtss:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: sub [[REG1:r[0-9]+]], r4, r3
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; CHECK-NEXT: rldicl r3, [[REG1]], 1, 63
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i16 %a, %b
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%conv2 = zext i1 %cmp to i32
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ret i32 %conv2
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @test_igtss_sext(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: test_igtss_sext:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3
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; CHECK-NEXT: sradi r3, [[REG]], 63
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i16 %a, %b
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%sub = sext i1 %cmp to i32
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ret i32 %sub
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}
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; FIXME
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @test_igtss_z(i16 signext %a) {
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; CHECK-LABEL: test_igtss_z:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: neg r3, r3
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; CHECK-NEXT: rldicl r3, r3, 1, 63
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i16 %a, 0
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%conv1 = zext i1 %cmp to i32
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ret i32 %conv1
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @test_igtss_sext_z(i16 signext %a) {
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; CHECK-LABEL: test_igtss_sext_z:
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; CHECK: # %bb.0: # %entry
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; CHECK: neg [[REG2:r[0-9]+]], r3
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; CHECK-NEXT: sradi r3, [[REG2]], 63
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i16 %a, 0
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%sub = sext i1 %cmp to i32
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ret i32 %sub
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}
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; Function Attrs: norecurse nounwind
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define void @test_igtss_store(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: test_igtss_store:
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; CHECK: # %bb.0: # %entry
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; CHECK: sub [[REG1:r[0-9]+]], r4, r3
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; CHECK: rldicl {{r[0-9]+}}, [[REG1]], 1, 63
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entry:
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%cmp = icmp sgt i16 %a, %b
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%conv3 = zext i1 %cmp to i16
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store i16 %conv3, i16* @glob, align 2
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @test_igtss_sext_store(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: test_igtss_sext_store:
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; CHECK: # %bb.0: # %entry
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; CHECK: sub [[REG:r[0-9]+]], r4, r3
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; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
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entry:
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%cmp = icmp sgt i16 %a, %b
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%conv3 = sext i1 %cmp to i16
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store i16 %conv3, i16* @glob, align 2
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ret void
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}
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; FIXME
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; Function Attrs: norecurse nounwind
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define void @test_igtss_z_store(i16 signext %a) {
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; CHECK-LABEL: test_igtss_z_store:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
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; CHECK-NEXT: neg r3, r3
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; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
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; CHECK-NEXT: rldicl r3, r3, 1, 63
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; CHECK-NEXT: sth r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i16 %a, 0
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%conv2 = zext i1 %cmp to i16
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store i16 %conv2, i16* @glob, align 2
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @test_igtss_sext_z_store(i16 signext %a) {
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; CHECK-LABEL: test_igtss_sext_z_store:
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; CHECK: neg [[REG2:r[0-9]+]], r3
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; CHECK: sradi {{r[0-9]+}}, [[REG2]], 63
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entry:
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%cmp = icmp sgt i16 %a, 0
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%conv2 = sext i1 %cmp to i16
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store i16 %conv2, i16* @glob, align 2
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ret void
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}
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