forked from OSchip/llvm-project
393 lines
12 KiB
LLVM
393 lines
12 KiB
LLVM
; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
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; RUN: -enable-ppc-quad-precision -verify-machineinstrs \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
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; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown \
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; RUN: -enable-ppc-quad-precision -verify-machineinstrs \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \
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; RUN: | FileCheck -check-prefix=CHECK-BE %s
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; Testing homogeneous aggregates.
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%struct.With9fp128params = type { fp128, fp128, fp128, fp128, fp128, fp128,
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fp128, fp128, fp128 }
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@a1 = common local_unnamed_addr global [3 x fp128] zeroinitializer, align 16
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; Function Attrs: norecurse nounwind readonly
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define fp128 @testArray_01(fp128* nocapture readonly %sa) {
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; CHECK-LABEL: testArray_01:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxv v2, 32(r3)
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: testArray_01:
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; CHECK-BE: lxv v2, 32(r3)
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; CHECK-BE-NEXT: blr
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entry:
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%arrayidx = getelementptr inbounds fp128, fp128* %sa, i64 2
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%0 = load fp128, fp128* %arrayidx, align 16
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ret fp128 %0
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}
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; Function Attrs: norecurse nounwind readonly
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define fp128 @testArray_02() {
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; CHECK-LABEL: testArray_02:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis r3, r2, .LC0@toc@ha
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; CHECK-NEXT: ld r3, .LC0@toc@l(r3)
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; CHECK-NEXT: lxv v2, 32(r3)
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: testArray_02:
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; CHECK-BE: lxv v2, 32(r3)
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; CHECK-BE-NEXT: blr
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entry:
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%0 = load fp128, fp128* getelementptr inbounds ([3 x fp128], [3 x fp128]* @a1,
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i64 0, i64 2), align 16
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ret fp128 %0
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}
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; Function Attrs: norecurse nounwind readnone
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define fp128 @testStruct_01(fp128 inreg returned %a.coerce) {
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; CHECK-LABEL: testStruct_01:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: testStruct_01:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: blr
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entry:
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ret fp128 %a.coerce
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}
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; Function Attrs: norecurse nounwind readnone
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define fp128 @testStruct_02([8 x fp128] %a.coerce) {
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; CHECK-LABEL: testStruct_02:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vmr v2, v9
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: testStruct_02:
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; CHECK-BE: vmr v2, v9
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; CHECK-BE-NEXT: blr
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entry:
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%a.coerce.fca.7.extract = extractvalue [8 x fp128] %a.coerce, 7
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ret fp128 %a.coerce.fca.7.extract
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}
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; Since we can only pass a max of 8 float128 value in VSX registers, ensure we
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; store to stack if passing more.
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; Function Attrs: norecurse nounwind readonly
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define fp128 @testStruct_03(%struct.With9fp128params* byval nocapture readonly
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align 16 %a) {
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; CHECK-LABEL: testStruct_03:
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; CHECK: # %bb.0: # %entry
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; CHECK-DAG: std r10, 88(r1)
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; CHECK-DAG: std r9, 80(r1)
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; CHECK-DAG: std r8, 72(r1)
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; CHECK-DAG: std r7, 64(r1)
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; CHECK-DAG: std r6, 56(r1)
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; CHECK-DAG: std r5, 48(r1)
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; CHECK-DAG: std r4, 40(r1)
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; CHECK-DAG: std r3, 32(r1)
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; CHECK-NEXT: lxv v2, 128(r1)
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: testStruct_03:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-DAG: std r10, 104(r1)
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; CHECK-BE-DAG: std r9, 96(r1)
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; CHECK-BE-DAG: std r8, 88(r1)
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; CHECK-BE-DAG: std r7, 80(r1)
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; CHECK-BE-DAG: std r6, 72(r1)
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; CHECK-BE-DAG: std r5, 64(r1)
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; CHECK-BE-DAG: std r4, 56(r1)
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; CHECK-BE-DAG: std r3, 48(r1)
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; CHECK-BE-NEXT: lxv v2, 144(r1)
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; CHECK-BE-NEXT: blr
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entry:
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%a7 = getelementptr inbounds %struct.With9fp128params,
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%struct.With9fp128params* %a, i64 0, i32 6
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%0 = load fp128, fp128* %a7, align 16
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ret fp128 %0
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}
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; Function Attrs: norecurse nounwind readnone
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define fp128 @testStruct_04([8 x fp128] %a.coerce) {
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; CHECK-LABEL: testStruct_04:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vmr v2, v5
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: testStruct_04:
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; CHECK-BE: vmr v2, v5
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; CHECK-BE-NEXT: blr
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entry:
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%a.coerce.fca.3.extract = extractvalue [8 x fp128] %a.coerce, 3
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ret fp128 %a.coerce.fca.3.extract
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}
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; Function Attrs: norecurse nounwind readnone
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define fp128 @testHUnion_01([1 x fp128] %a.coerce) {
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; CHECK-LABEL: testHUnion_01:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: testHUnion_01:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: blr
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entry:
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%a.coerce.fca.0.extract = extractvalue [1 x fp128] %a.coerce, 0
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ret fp128 %a.coerce.fca.0.extract
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}
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; Function Attrs: norecurse nounwind readnone
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define fp128 @testHUnion_02([3 x fp128] %a.coerce) {
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; CHECK-LABEL: testHUnion_02:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: testHUnion_02:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: blr
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entry:
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%a.coerce.fca.0.extract = extractvalue [3 x fp128] %a.coerce, 0
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ret fp128 %a.coerce.fca.0.extract
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}
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; Function Attrs: norecurse nounwind readnone
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define fp128 @testHUnion_03([3 x fp128] %a.coerce) {
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; CHECK-LABEL: testHUnion_03:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vmr v2, v3
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: testHUnion_03:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: vmr v2, v3
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; CHECK-BE-NEXT: blr
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entry:
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%a.coerce.fca.1.extract = extractvalue [3 x fp128] %a.coerce, 1
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ret fp128 %a.coerce.fca.1.extract
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}
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; Function Attrs: norecurse nounwind readnone
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define fp128 @testHUnion_04([3 x fp128] %a.coerce) {
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; CHECK-LABEL: testHUnion_04:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vmr v2, v4
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: testHUnion_04:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: vmr v2, v4
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; CHECK-BE-NEXT: blr
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entry:
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%a.coerce.fca.2.extract = extractvalue [3 x fp128] %a.coerce, 2
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ret fp128 %a.coerce.fca.2.extract
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}
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; Testing mixed member aggregates.
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%struct.MixedC = type { i32, %struct.SA, float, [12 x i8] }
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%struct.SA = type { double, fp128, <4 x float> }
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; Function Attrs: norecurse nounwind readnone
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define fp128 @testMixedAggregate([3 x i128] %a.coerce) {
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; CHECK-LABEL: testMixedAggregate:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrdd v2, r8, r7
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: testMixedAggregate:
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; CHECK-BE: mtvsrdd v2, r8, r7
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; CHECK-BE-NEXT: blr
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entry:
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%a.coerce.fca.2.extract = extractvalue [3 x i128] %a.coerce, 2
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%0 = bitcast i128 %a.coerce.fca.2.extract to fp128
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ret fp128 %0
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}
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; Function Attrs: norecurse nounwind readnone
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define fp128 @testMixedAggregate_02([4 x i128] %a.coerce) {
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; CHECK-LABEL: testMixedAggregate_02:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrdd v2, r6, r5
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: testMixedAggregate_02:
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; CHECK-BE: mtvsrdd v2, r6, r5
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; CHECK-BE-NEXT: blr
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entry:
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%a.coerce.fca.1.extract = extractvalue [4 x i128] %a.coerce, 1
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%0 = bitcast i128 %a.coerce.fca.1.extract to fp128
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ret fp128 %0
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}
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; Function Attrs: norecurse nounwind readnone
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define fp128 @testMixedAggregate_03([4 x i128] %sa.coerce) {
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; CHECK-LABEL: testMixedAggregate_03:
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; CHECK: # %bb.0: # %entry
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; CHECK: mtvsrwa v2, r3
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; CHECK: xscvsdqp v2, v2
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; CHECK: mtvsrdd v3, r6, r5
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; CHECK: xsaddqp v2, v3, v2
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; CHECK: mtvsrd v[[REG1:[0-9]+]], r10
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; CHECK: xscvsdqp v[[REG:[0-9]+]], v[[REG1]]
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; CHECK: xsaddqp v2, v2, v[[REG]]
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; CHECK-NEXT: blr
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entry:
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%sa.coerce.fca.0.extract = extractvalue [4 x i128] %sa.coerce, 0
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%sa.sroa.0.0.extract.trunc = trunc i128 %sa.coerce.fca.0.extract to i32
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%sa.coerce.fca.1.extract = extractvalue [4 x i128] %sa.coerce, 1
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%sa.coerce.fca.3.extract = extractvalue [4 x i128] %sa.coerce, 3
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%sa.sroa.6.48.extract.shift = lshr i128 %sa.coerce.fca.3.extract, 64
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%sa.sroa.6.48.extract.trunc = trunc i128 %sa.sroa.6.48.extract.shift to i64
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%conv = sitofp i32 %sa.sroa.0.0.extract.trunc to fp128
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%0 = bitcast i128 %sa.coerce.fca.1.extract to fp128
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%add = fadd fp128 %0, %conv
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%conv2 = sitofp i64 %sa.sroa.6.48.extract.trunc to fp128
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%add3 = fadd fp128 %add, %conv2
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ret fp128 %add3
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}
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; Function Attrs: norecurse nounwind readonly
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define fp128 @testNestedAggregate(%struct.MixedC* byval nocapture readonly align 16 %a) {
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; CHECK-LABEL: testNestedAggregate:
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; CHECK: # %bb.0: # %entry
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; CHECK-DAG: std r10, 88(r1)
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; CHECK-DAG: std r9, 80(r1)
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; CHECK-DAG: std r8, 72(r1)
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; CHECK-DAG: std r7, 64(r1)
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; CHECK-DAG: std r6, 56(r1)
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; CHECK-DAG: std r5, 48(r1)
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; CHECK-DAG: std r4, 40(r1)
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; CHECK-DAG: std r3, 32(r1)
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; CHECK-NEXT: lxv v2, 64(r1)
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: testNestedAggregate:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-DAG: std r8, 88(r1)
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; CHECK-BE-DAG: std r7, 80(r1)
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; CHECK-BE-DAG: std r10, 104(r1)
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; CHECK-BE-DAG: std r9, 96(r1)
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; CHECK-BE-DAG: std r6, 72(r1)
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; CHECK-BE-DAG: std r5, 64(r1)
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; CHECK-BE-DAG: std r4, 56(r1)
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; CHECK-BE-DAG: std r3, 48(r1)
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; CHECK-BE-NEXT: lxv v2, 80(r1)
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; CHECK-BE-NEXT: blr
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entry:
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%c = getelementptr inbounds %struct.MixedC, %struct.MixedC* %a, i64 0, i32 1, i32 1
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%0 = load fp128, fp128* %c, align 16
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ret fp128 %0
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}
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; Function Attrs: norecurse nounwind readnone
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define fp128 @testUnion_01([1 x i128] %a.coerce) {
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; CHECK-LABEL: testUnion_01:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrdd v2, r4, r3
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: testUnion_01:
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; CHECK-BE: mtvsrdd v2, r4, r3
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; CHECK-BE-NEXT: blr
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entry:
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%a.coerce.fca.0.extract = extractvalue [1 x i128] %a.coerce, 0
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%0 = bitcast i128 %a.coerce.fca.0.extract to fp128
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ret fp128 %0
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}
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; Function Attrs: norecurse nounwind readnone
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define fp128 @testUnion_02([1 x i128] %a.coerce) {
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; CHECK-LABEL: testUnion_02:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrdd v2, r4, r3
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: testUnion_02:
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; CHECK-BE: mtvsrdd v2, r4, r3
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; CHECK-BE-NEXT: blr
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entry:
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%a.coerce.fca.0.extract = extractvalue [1 x i128] %a.coerce, 0
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%0 = bitcast i128 %a.coerce.fca.0.extract to fp128
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ret fp128 %0
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}
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; Function Attrs: norecurse nounwind readnone
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define fp128 @testUnion_03([4 x i128] %a.coerce) {
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; CHECK-LABEL: testUnion_03:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrdd v2, r8, r7
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: testUnion_03:
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; CHECK-BE: mtvsrdd v2, r8, r7
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; CHECK-BE-NEXT: blr
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entry:
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%a.coerce.fca.2.extract = extractvalue [4 x i128] %a.coerce, 2
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%0 = bitcast i128 %a.coerce.fca.2.extract to fp128
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ret fp128 %0
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}
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; Function Attrs: nounwind
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define fp128 @sum_float128(i32 signext %count, ...) {
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; CHECK-LABEL: sum_float128:
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; CHECK: # %bb.0: # %entry
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; CHECK-DAG: std r10, 88(r1)
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; CHECK-DAG: std r9, 80(r1)
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; CHECK-DAG: std r8, 72(r1)
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; CHECK-DAG: std r7, 64(r1)
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; CHECK-DAG: std r6, 56(r1)
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; CHECK-DAG: std r4, 40(r1)
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; CHECK-DAG: cmpwi cr0, r3, 1
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; CHECK-DAG: std r5, 48(r1)
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; CHECK-DAG: addis [[REG:r[0-9]+]], r2, .LCPI17_0@toc@ha
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; CHECK-DAG: addi [[REG1:r[0-9]+]], [[REG]], .LCPI17_0@toc@l
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; CHECK-DAG: lxvx v2, 0, [[REG1]]
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; CHECK-NEXT: bltlr cr0
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; CHECK-NEXT: # %bb.1: # %if.end
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; CHECK-NEXT: addi r3, r1, 40
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; CHECK-NEXT: lxvx v3, 0, r3
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; CHECK-NEXT: xsaddqp v2, v3, v2
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; CHECK-NEXT: addi [[REG2:r[0-9]+]], r1, 72
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; CHECK-NEXT: std [[REG2]], -8(r1)
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; CHECK-NEXT: lxv v3, 16(r3)
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; CHECK-NEXT: xsaddqp v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%ap = alloca i8*, align 8
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%0 = bitcast i8** %ap to i8*
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call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %0) #2
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%cmp = icmp slt i32 %count, 1
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br i1 %cmp, label %cleanup, label %if.end
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if.end: ; preds = %entry
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call void @llvm.va_start(i8* nonnull %0)
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%argp.cur = load i8*, i8** %ap, align 8
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%argp.next = getelementptr inbounds i8, i8* %argp.cur, i64 16
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%1 = bitcast i8* %argp.cur to fp128*
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%2 = load fp128, fp128* %1, align 8
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%add = fadd fp128 %2, 0xL00000000000000000000000000000000
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%argp.next3 = getelementptr inbounds i8, i8* %argp.cur, i64 32
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store i8* %argp.next3, i8** %ap, align 8
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%3 = bitcast i8* %argp.next to fp128*
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%4 = load fp128, fp128* %3, align 8
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%add4 = fadd fp128 %add, %4
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call void @llvm.va_end(i8* nonnull %0)
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br label %cleanup
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cleanup: ; preds = %entry, %if.end
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%retval.0 = phi fp128 [ %add4, %if.end ], [ 0xL00000000000000000000000000000000, %entry ]
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call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %0) #2
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ret fp128 %retval.0
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}
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declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1
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declare void @llvm.va_start(i8*) #2
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declare void @llvm.va_end(i8*) #2
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declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1
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