llvm-project/llvm/test/CodeGen/AArch64/uadd_sat.ll

39 lines
1.1 KiB
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
declare i4 @llvm.uadd.sat.i4 (i4, i4)
declare i32 @llvm.uadd.sat.i32 (i32, i32)
declare i64 @llvm.uadd.sat.i64 (i64, i64)
define i32 @func(i32 %x, i32 %y) nounwind {
; CHECK-LABEL: func:
; CHECK: // %bb.0:
; CHECK-NEXT: adds w8, w0, w1
; CHECK-NEXT: csinv w0, w8, wzr, lo
; CHECK-NEXT: ret
%tmp = call i32 @llvm.uadd.sat.i32(i32 %x, i32 %y);
ret i32 %tmp;
}
define i64 @func2(i64 %x, i64 %y) nounwind {
; CHECK-LABEL: func2:
; CHECK: // %bb.0:
; CHECK-NEXT: adds x8, x0, x1
; CHECK-NEXT: csinv x0, x8, xzr, lo
; CHECK-NEXT: ret
%tmp = call i64 @llvm.uadd.sat.i64(i64 %x, i64 %y);
ret i64 %tmp;
}
define i4 @func3(i4 %x, i4 %y) nounwind {
; CHECK-LABEL: func3:
; CHECK: // %bb.0:
; CHECK-NEXT: lsl w8, w0, #28
; CHECK-NEXT: adds w8, w8, w1, lsl #28
; CHECK-NEXT: csinv w8, w8, wzr, lo
; CHECK-NEXT: lsr w0, w8, #28
; CHECK-NEXT: ret
%tmp = call i4 @llvm.uadd.sat.i4(i4 %x, i4 %y);
ret i4 %tmp;
}