forked from OSchip/llvm-project
615 lines
15 KiB
YAML
615 lines
15 KiB
YAML
# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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define void @test_trunc_and_zext_s1_to_s32() { ret void }
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define void @test_trunc_and_sext_s1_to_s32() { ret void }
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define void @test_trunc_and_anyext_s1_to_s32() { ret void }
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define void @test_trunc_and_zext_s8_to_s32() { ret void }
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define void @test_trunc_and_sext_s8_to_s32() { ret void }
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define void @test_trunc_and_anyext_s8_to_s32() { ret void }
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define void @test_trunc_and_zext_s16_to_s32() { ret void }
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define void @test_trunc_and_sext_s16_to_s32() { ret void }
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define void @test_trunc_and_anyext_s16_to_s32() { ret void }
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define void @test_trunc_and_zext_s1_to_s16() { ret void }
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define void @test_trunc_and_sext_s1_to_s16() { ret void }
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define void @test_trunc_and_anyext_s1_to_s16() { ret void }
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define void @test_trunc_and_zext_s8_to_s16() { ret void }
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define void @test_trunc_and_sext_s8_to_s16() { ret void }
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define void @test_trunc_and_anyext_s8_to_s16() { ret void }
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define void @test_trunc_and_zext_s1_to_s8() { ret void }
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define void @test_trunc_and_sext_s1_to_s8() { ret void }
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define void @test_trunc_and_anyext_s1_to_s8() { ret void }
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...
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---
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name: test_trunc_and_zext_s1_to_s32
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# CHECK-LABEL: name: test_trunc_and_zext_s1_to_s32
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(s32) = COPY $r0
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; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
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%1(s1) = G_TRUNC %0(s32)
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%2(s32) = G_ZEXT %1(s1)
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; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]]
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; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2ANDri [[RVREG]], 1, 14, $noreg, $noreg
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$r0 = COPY %2(s32)
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; CHECK: $r0 = COPY [[VREGEXT]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_trunc_and_sext_s1_to_s32
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# CHECK-LABEL: name: test_trunc_and_sext_s1_to_s32
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(s32) = COPY $r0
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; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
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%1(s1) = G_TRUNC %0(s32)
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%2(s32) = G_SEXT %1(s1)
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; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]]
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; CHECK: [[VREGAND:%[0-9]+]]:rgpr = t2ANDri [[RVREG]], 1, 14, $noreg, $noreg
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; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2RSBri [[VREGAND]], 0, 14, $noreg, $noreg
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$r0 = COPY %2(s32)
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; CHECK: $r0 = COPY [[VREGEXT]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_trunc_and_anyext_s1_to_s32
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# CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s32
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(s32) = COPY $r0
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; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
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%1(s1) = G_TRUNC %0(s32)
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%2(s32) = G_ANYEXT %1(s1)
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$r0 = COPY %2(s32)
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; CHECK: $r0 = COPY [[VREG]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_trunc_and_zext_s8_to_s32
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# CHECK-LABEL: name: test_trunc_and_zext_s8_to_s32
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(s32) = COPY $r0
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; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
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%1(s8) = G_TRUNC %0(s32)
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; CHECK: [[VREGTRUNC:%[0-9]+]]:rgpr = COPY [[VREG]]
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%2(s32) = G_ZEXT %1(s8)
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; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2UXTB [[VREGTRUNC]], 0, 14, $noreg
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$r0 = COPY %2(s32)
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; CHECK: $r0 = COPY [[VREGEXT]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_trunc_and_sext_s8_to_s32
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# CHECK-LABEL: name: test_trunc_and_sext_s8_to_s32
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(s32) = COPY $r0
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; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
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%1(s8) = G_TRUNC %0(s32)
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; CHECK: [[VREGTRUNC:%[0-9]+]]:rgpr = COPY [[VREG]]
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%2(s32) = G_SEXT %1(s8)
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; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2SXTB [[VREGTRUNC]], 0, 14, $noreg
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$r0 = COPY %2(s32)
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; CHECK: $r0 = COPY [[VREGEXT]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_trunc_and_anyext_s8_to_s32
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# CHECK-LABEL: name: test_trunc_and_anyext_s8_to_s32
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(s32) = COPY $r0
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; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
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%1(s8) = G_TRUNC %0(s32)
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%2(s32) = G_ANYEXT %1(s8)
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$r0 = COPY %2(s32)
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; CHECK: $r0 = COPY [[VREG]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_trunc_and_zext_s16_to_s32
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# CHECK-LABEL: name: test_trunc_and_zext_s16_to_s32
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(s32) = COPY $r0
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; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
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%1(s16) = G_TRUNC %0(s32)
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; CHECK: [[VREGTRUNC:%[0-9]+]]:rgpr = COPY [[VREG]]
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%2(s32) = G_ZEXT %1(s16)
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; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2UXTH [[VREGTRUNC]], 0, 14, $noreg
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$r0 = COPY %2(s32)
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; CHECK: $r0 = COPY [[VREGEXT]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_trunc_and_sext_s16_to_s32
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# CHECK-LABEL: name: test_trunc_and_sext_s16_to_s32
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(s32) = COPY $r0
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; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
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%1(s16) = G_TRUNC %0(s32)
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; CHECK: [[VREGTRUNC:%[0-9]+]]:rgpr = COPY [[VREG]]
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%2(s32) = G_SEXT %1(s16)
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; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2SXTH [[VREGTRUNC]], 0, 14, $noreg
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$r0 = COPY %2(s32)
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; CHECK: $r0 = COPY [[VREGEXT]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_trunc_and_anyext_s16_to_s32
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# CHECK-LABEL: name: test_trunc_and_anyext_s16_to_s32
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(s32) = COPY $r0
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; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
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%1(s16) = G_TRUNC %0(s32)
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%2(s32) = G_ANYEXT %1(s16)
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$r0 = COPY %2(s32)
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; CHECK: $r0 = COPY [[VREG]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_trunc_and_zext_s1_to_s16
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# CHECK-LABEL: name: test_trunc_and_zext_s1_to_s16
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1
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%0(p0) = COPY $r0
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; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
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%1(s32) = COPY $r1
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; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
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%2(s1) = G_TRUNC %1(s32)
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%3(s16) = G_ZEXT %2(s1)
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; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]]
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; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2ANDri [[RVREG]], 1, 14, $noreg, $noreg
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G_STORE %3(s16), %0(p0) :: (store 2)
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; CHECK: t2STRHi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 2)
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BX_RET 14, $noreg
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; CHECK: BX_RET 14, $noreg
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...
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---
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name: test_trunc_and_sext_s1_to_s16
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# CHECK-LABEL: name: test_trunc_and_sext_s1_to_s16
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1
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%0(p0) = COPY $r0
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; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
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%1(s32) = COPY $r1
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; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
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%2(s1) = G_TRUNC %1(s32)
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%3(s16) = G_SEXT %2(s1)
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; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]]
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; CHECK: [[VREGAND:%[0-9]+]]:rgpr = t2ANDri [[RVREG]], 1, 14, $noreg, $noreg
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; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2RSBri [[VREGAND]], 0, 14, $noreg, $noreg
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G_STORE %3(s16), %0(p0) :: (store 2)
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; CHECK: t2STRHi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 2)
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BX_RET 14, $noreg
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; CHECK: BX_RET 14, $noreg
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...
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---
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name: test_trunc_and_anyext_s1_to_s16
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# CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s16
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1
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%0(p0) = COPY $r0
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; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
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%1(s32) = COPY $r1
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; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
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%2(s1) = G_TRUNC %1(s32)
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%3(s16) = G_ANYEXT %2(s1)
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G_STORE %3(s16), %0(p0) :: (store 2)
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; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]]
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; CHECK: t2STRHi12 [[RVREG]], [[PTR]], 0, 14, $noreg :: (store 2)
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BX_RET 14, $noreg
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; CHECK: BX_RET 14, $noreg
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...
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---
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name: test_trunc_and_zext_s8_to_s16
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# CHECK-LABEL: name: test_trunc_and_zext_s8_to_s16
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1
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%0(p0) = COPY $r0
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; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
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%1(s32) = COPY $r1
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; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
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%2(s8) = G_TRUNC %1(s32)
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; CHECK: [[VREGTRUNC:%[1-9]+]]:rgpr = COPY [[VREG]]
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%3(s16) = G_ZEXT %2(s8)
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; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2UXTB [[VREGTRUNC]], 0, 14, $noreg
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G_STORE %3(s16), %0(p0) :: (store 2)
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; CHECK: t2STRHi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 2)
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BX_RET 14, $noreg
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; CHECK: BX_RET 14, $noreg
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...
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---
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name: test_trunc_and_sext_s8_to_s16
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# CHECK-LABEL: name: test_trunc_and_sext_s8_to_s16
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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body: |
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bb.0:
|
|
liveins: $r0, $r1
|
|
|
|
%0(p0) = COPY $r0
|
|
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
|
|
|
|
%1(s32) = COPY $r1
|
|
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
|
|
|
|
%2(s8) = G_TRUNC %1(s32)
|
|
; CHECK: [[VREGTRUNC:%[1-9]+]]:rgpr = COPY [[VREG]]
|
|
|
|
%3(s16) = G_SEXT %2(s8)
|
|
; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2SXTB [[VREGTRUNC]], 0, 14, $noreg
|
|
|
|
G_STORE %3(s16), %0(p0) :: (store 2)
|
|
; CHECK: t2STRHi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 2)
|
|
|
|
BX_RET 14, $noreg
|
|
; CHECK: BX_RET 14, $noreg
|
|
...
|
|
---
|
|
name: test_trunc_and_anyext_s8_to_s16
|
|
# CHECK-LABEL: name: test_trunc_and_anyext_s8_to_s16
|
|
legalized: true
|
|
regBankSelected: true
|
|
selected: false
|
|
# CHECK: selected: true
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: gprb }
|
|
- { id: 1, class: gprb }
|
|
- { id: 2, class: gprb }
|
|
- { id: 3, class: gprb }
|
|
body: |
|
|
bb.0:
|
|
liveins: $r0, $r1
|
|
|
|
%0(p0) = COPY $r0
|
|
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
|
|
|
|
%1(s32) = COPY $r1
|
|
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
|
|
|
|
%2(s8) = G_TRUNC %1(s32)
|
|
|
|
%3(s16) = G_ANYEXT %2(s8)
|
|
|
|
G_STORE %3(s16), %0(p0) :: (store 2)
|
|
; CHECK: [[VREGR:%[0-9]+]]:rgpr = COPY [[VREG]]
|
|
; CHECK: t2STRHi12 [[VREGR]], [[PTR]], 0, 14, $noreg :: (store 2)
|
|
|
|
BX_RET 14, $noreg
|
|
; CHECK: BX_RET 14, $noreg
|
|
...
|
|
---
|
|
name: test_trunc_and_zext_s1_to_s8
|
|
# CHECK-LABEL: name: test_trunc_and_zext_s1_to_s8
|
|
legalized: true
|
|
regBankSelected: true
|
|
selected: false
|
|
# CHECK: selected: true
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: gprb }
|
|
- { id: 1, class: gprb }
|
|
- { id: 2, class: gprb }
|
|
- { id: 3, class: gprb }
|
|
body: |
|
|
bb.0:
|
|
liveins: $r0, $r1
|
|
|
|
%0(p0) = COPY $r0
|
|
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
|
|
|
|
%1(s32) = COPY $r1
|
|
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
|
|
|
|
%2(s1) = G_TRUNC %1(s32)
|
|
|
|
%3(s8) = G_ZEXT %2(s1)
|
|
; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]]
|
|
; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2ANDri [[RVREG]], 1, 14, $noreg, $noreg
|
|
|
|
G_STORE %3(s8), %0(p0) :: (store 1)
|
|
; CHECK: t2STRBi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 1)
|
|
|
|
BX_RET 14, $noreg
|
|
; CHECK: BX_RET 14, $noreg
|
|
...
|
|
---
|
|
name: test_trunc_and_sext_s1_to_s8
|
|
# CHECK-LABEL: name: test_trunc_and_sext_s1_to_s8
|
|
legalized: true
|
|
regBankSelected: true
|
|
selected: false
|
|
# CHECK: selected: true
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: gprb }
|
|
- { id: 1, class: gprb }
|
|
- { id: 2, class: gprb }
|
|
- { id: 3, class: gprb }
|
|
body: |
|
|
bb.0:
|
|
liveins: $r0, $r1
|
|
|
|
%0(p0) = COPY $r0
|
|
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
|
|
|
|
%1(s32) = COPY $r1
|
|
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
|
|
|
|
%2(s1) = G_TRUNC %1(s32)
|
|
|
|
%3(s8) = G_SEXT %2(s1)
|
|
; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]]
|
|
; CHECK: [[VREGAND:%[0-9]+]]:rgpr = t2ANDri [[RVREG]], 1, 14, $noreg, $noreg
|
|
; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2RSBri [[VREGAND]], 0, 14, $noreg, $noreg
|
|
|
|
G_STORE %3(s8), %0(p0) :: (store 1)
|
|
; CHECK: t2STRBi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 1)
|
|
|
|
BX_RET 14, $noreg
|
|
; CHECK: BX_RET 14, $noreg
|
|
...
|
|
---
|
|
name: test_trunc_and_anyext_s1_to_s8
|
|
# CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s8
|
|
legalized: true
|
|
regBankSelected: true
|
|
selected: false
|
|
# CHECK: selected: true
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: gprb }
|
|
- { id: 1, class: gprb }
|
|
- { id: 2, class: gprb }
|
|
- { id: 3, class: gprb }
|
|
body: |
|
|
bb.0:
|
|
liveins: $r0, $r1
|
|
|
|
%0(p0) = COPY $r0
|
|
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
|
|
|
|
%1(s32) = COPY $r1
|
|
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
|
|
|
|
%2(s1) = G_TRUNC %1(s32)
|
|
|
|
%3(s8) = G_ANYEXT %2(s1)
|
|
|
|
G_STORE %3(s8), %0(p0) :: (store 1)
|
|
; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]]
|
|
; CHECK: t2STRBi12 [[RVREG]], [[PTR]], 0, 14, $noreg :: (store 1)
|
|
|
|
BX_RET 14, $noreg
|
|
; CHECK: BX_RET 14, $noreg
|
|
...
|