forked from OSchip/llvm-project
148 lines
3.9 KiB
YAML
148 lines
3.9 KiB
YAML
# RUN: llc -O0 -mtriple arm-- -mattr=+v6 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,ARM
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# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,THUMB
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--- |
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define void @test_shifts_to_revsh() { ret void }
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define void @test_shifts_to_revsh_commutative() { ret void }
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define void @test_shifts_no_revsh_constants() { ret void }
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...
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---
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name: test_shifts_to_revsh
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# CHECK-LABEL: name: test_shifts_to_revsh
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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- { id: 4, class: gprb }
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- { id: 5, class: gprb }
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- { id: 6, class: gprb }
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- { id: 7, class: gprb }
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- { id: 8, class: gprb }
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- { id: 9, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(s32) = COPY $r0
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; ARM: [[VREGX:%[0-9]+]]:gpr = COPY $r0
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; THUMB: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
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%1(s32) = G_CONSTANT i32 24
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%2(s32) = G_SHL %0(s32), %1(s32)
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%3(s32) = G_CONSTANT i32 16
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%4(s32) = G_ASHR %2(s32), %3(s32)
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%5(s32) = G_CONSTANT i32 8
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%6(s32) = G_LSHR %0(s32), %5(s32)
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%7(s32) = G_CONSTANT i32 255
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%8(s32) = G_AND %6(s32), %7(s32)
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%9(s32) = G_OR %4(s32), %8(s32)
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; ARM: [[VREGR:%[0-9]+]]:gpr = REVSH [[VREGX]]
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; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2REVSH [[VREGX]]
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$r0 = COPY %9(s32)
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; CHECK: $r0 = COPY [[VREGR]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_shifts_to_revsh_commutative
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# CHECK-LABEL: name: test_shifts_to_revsh_commutative
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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- { id: 4, class: gprb }
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- { id: 5, class: gprb }
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- { id: 6, class: gprb }
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- { id: 7, class: gprb }
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- { id: 8, class: gprb }
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- { id: 9, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(s32) = COPY $r0
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; ARM: [[VREGX:%[0-9]+]]:gpr = COPY $r0
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; THUMB: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
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%1(s32) = G_CONSTANT i32 24
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%2(s32) = G_SHL %0(s32), %1(s32)
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%3(s32) = G_CONSTANT i32 16
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%4(s32) = G_ASHR %2(s32), %3(s32)
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%5(s32) = G_CONSTANT i32 8
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%6(s32) = G_LSHR %0(s32), %5(s32)
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%7(s32) = G_CONSTANT i32 255
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%8(s32) = G_AND %6(s32), %7(s32)
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%9(s32) = G_OR %8(s32), %4(s32)
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; ARM: [[VREGR:%[0-9]+]]:gpr = REVSH [[VREGX]]
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; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2REVSH [[VREGX]]
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$r0 = COPY %9(s32)
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; CHECK: $r0 = COPY [[VREGR]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_shifts_no_revsh_constants
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# CHECK-LABEL: name: test_shifts_no_revsh_constants
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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- { id: 4, class: gprb }
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- { id: 5, class: gprb }
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- { id: 6, class: gprb }
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- { id: 7, class: gprb }
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- { id: 8, class: gprb }
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- { id: 9, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(s32) = COPY $r0
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%1(s32) = G_CONSTANT i32 16 ; REVSH needs 24 here
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%2(s32) = G_SHL %0(s32), %1(s32)
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%3(s32) = G_CONSTANT i32 24 ; REVSH needs 16 here
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%4(s32) = G_ASHR %2(s32), %3(s32)
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%5(s32) = G_CONSTANT i32 8
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%6(s32) = G_LSHR %0(s32), %5(s32)
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%7(s32) = G_CONSTANT i32 255
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%8(s32) = G_AND %6(s32), %7(s32)
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%9(s32) = G_OR %4(s32), %8(s32)
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; We don't really care how this is folded as long as it's not into a REVSH.
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; CHECK-NOT: REVSH
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$r0 = COPY %9(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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