forked from OSchip/llvm-project
266 lines
11 KiB
LLVM
266 lines
11 KiB
LLVM
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -enable-misched=0 -post-RA-scheduler=0 -stress-regalloc=8 < %s | FileCheck %s
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; Test that the VGPR spiller correctly switches to SGPR offsets when the
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; instruction offset field would overflow, and that it accounts for memory
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; swizzling.
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; CHECK-LABEL: test_inst_offset_kernel
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define amdgpu_kernel void @test_inst_offset_kernel() {
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entry:
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; Occupy 4092 bytes of scratch, so the offset of the spill of %a just fits in
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; the instruction offset field.
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%alloca = alloca i8, i32 4088, align 4, addrspace(5)
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%buf = bitcast i8 addrspace(5)* %alloca to i32 addrspace(5)*
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%aptr = getelementptr i32, i32 addrspace(5)* %buf, i32 1
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; CHECK: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 offset:4092 ; 4-byte Folded Spill
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%a = load volatile i32, i32 addrspace(5)* %aptr
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; Force %a to spill.
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call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}" ()
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%outptr = getelementptr i32, i32 addrspace(5)* %buf, i32 1
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store volatile i32 %a, i32 addrspace(5)* %outptr
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ret void
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}
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; CHECK-LABEL: test_sgpr_offset_kernel
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define amdgpu_kernel void @test_sgpr_offset_kernel() {
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entry:
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; Occupy 4096 bytes of scratch, so the offset of the spill of %a does not
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; fit in the instruction, and has to live in the SGPR offset.
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%alloca = alloca i8, i32 4092, align 4, addrspace(5)
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%buf = bitcast i8 addrspace(5)* %alloca to i32 addrspace(5)*
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%aptr = getelementptr i32, i32 addrspace(5)* %buf, i32 1
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; 0x40000 / 64 = 4096 (for wave64)
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; CHECK: s_mov_b32 s6, 0x40000
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; CHECK: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s6 ; 4-byte Folded Spill
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%a = load volatile i32, i32 addrspace(5)* %aptr
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; Force %a to spill
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call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}" ()
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%outptr = getelementptr i32, i32 addrspace(5)* %buf, i32 1
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store volatile i32 %a, i32 addrspace(5)* %outptr
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ret void
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}
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; FIXME: If we fail to scavenge an SGPR in a kernel we don't have a stack
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; pointer to temporarily update, so we just crash.
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; CHECK-LABEL: test_sgpr_offset_function_scavenge_fail
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define void @test_sgpr_offset_function_scavenge_fail() #2 {
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entry:
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; Occupy 4096 bytes of scratch, so the offset of the spill of %a does not
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; fit in the instruction, and has to live in the SGPR offset.
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%alloca = alloca i8, i32 4096, align 4, addrspace(5)
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%buf = bitcast i8 addrspace(5)* %alloca to i32 addrspace(5)*
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%aptr = getelementptr i32, i32 addrspace(5)* %buf, i32 1
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%asm.0 = call { i32, i32, i32, i32, i32, i32, i32, i32 } asm sideeffect "", "=s,=s,=s,=s,=s,=s,=s,=s"()
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%asm0.0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm.0, 0
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%asm1.0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm.0, 1
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%asm2.0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm.0, 2
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%asm3.0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm.0, 3
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%asm4.0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm.0, 4
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%asm5.0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm.0, 5
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%asm6.0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm.0, 6
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%asm7.0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm.0, 7
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; 0x40000 / 64 = 4096 (for wave64)
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%a = load volatile i32, i32 addrspace(5)* %aptr
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; CHECK: s_add_u32 s32, s32, 0x40000
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; CHECK: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s32 ; 4-byte Folded Spill
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; CHECK: s_sub_u32 s32, s32, 0x40000
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call void asm sideeffect "", "s,s,s,s,s,s,s,s,v"(i32 %asm0.0, i32 %asm1.0, i32 %asm2.0, i32 %asm3.0, i32 %asm4.0, i32 %asm5.0, i32 %asm6.0, i32 %asm7.0, i32 %a)
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%asm = call { i32, i32, i32, i32, i32, i32, i32, i32 } asm sideeffect "", "=s,=s,=s,=s,=s,=s,=s,=s"()
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%asm0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm, 0
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%asm1 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm, 1
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%asm2 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm, 2
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%asm3 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm, 3
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%asm4 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm, 4
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%asm5 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm, 5
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%asm6 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm, 6
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%asm7 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm, 7
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call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}"() #0
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; CHECK: s_add_u32 s32, s32, 0x40000
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; CHECK: buffer_load_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s32 ; 4-byte Folded Reload
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; CHECK: s_sub_u32 s32, s32, 0x40000
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; Force %a to spill with no free SGPRs
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call void asm sideeffect "", "s,s,s,s,s,s,s,s,v"(i32 %asm0, i32 %asm1, i32 %asm2, i32 %asm3, i32 %asm4, i32 %asm5, i32 %asm6, i32 %asm7, i32 %a)
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ret void
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}
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; CHECK-LABEL: test_sgpr_offset_subregs_kernel
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define amdgpu_kernel void @test_sgpr_offset_subregs_kernel() {
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entry:
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; Occupy 4088 bytes of scratch, so that the spill of the last subreg of %a
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; still fits below offset 4096 (4088 + 8 - 4 = 4092), and can be placed in
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; the instruction offset field.
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%alloca = alloca i8, i32 4084, align 4, addrspace(5)
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%bufv1 = bitcast i8 addrspace(5)* %alloca to i32 addrspace(5)*
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%bufv2 = bitcast i8 addrspace(5)* %alloca to <2 x i32> addrspace(5)*
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; CHECK: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 offset:4088 ; 4-byte Folded Spill
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; CHECK: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 offset:4092 ; 4-byte Folded Spill
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%aptr = getelementptr <2 x i32>, <2 x i32> addrspace(5)* %bufv2, i32 1
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%a = load volatile <2 x i32>, <2 x i32> addrspace(5)* %aptr
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; Force %a to spill.
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call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}" ()
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; Ensure the alloca sticks around.
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%bptr = getelementptr i32, i32 addrspace(5)* %bufv1, i32 1
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%b = load volatile i32, i32 addrspace(5)* %bptr
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; Ensure the spill is of the full super-reg.
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call void asm sideeffect "; $0", "r"(<2 x i32> %a)
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ret void
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}
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; CHECK-LABEL: test_inst_offset_subregs_kernel
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define amdgpu_kernel void @test_inst_offset_subregs_kernel() {
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entry:
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; Occupy 4092 bytes of scratch, so that the spill of the last subreg of %a
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; does not fit below offset 4096 (4092 + 8 - 4 = 4096), and has to live
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; in the SGPR offset.
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%alloca = alloca i8, i32 4088, align 4, addrspace(5)
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%bufv1 = bitcast i8 addrspace(5)* %alloca to i32 addrspace(5)*
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%bufv2 = bitcast i8 addrspace(5)* %alloca to <2 x i32> addrspace(5)*
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; 0x3ff00 / 64 = 4092 (for wave64)
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; CHECK: s_mov_b32 s6, 0x3ff00
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; CHECK: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s6 ; 4-byte Folded Spill
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; CHECK: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s6 offset:4 ; 4-byte Folded Spill
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%aptr = getelementptr <2 x i32>, <2 x i32> addrspace(5)* %bufv2, i32 1
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%a = load volatile <2 x i32>, <2 x i32> addrspace(5)* %aptr
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; Force %a to spill.
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call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}" ()
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; Ensure the alloca sticks around.
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%bptr = getelementptr i32, i32 addrspace(5)* %bufv1, i32 1
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%b = load volatile i32, i32 addrspace(5)* %bptr
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; Ensure the spill is of the full super-reg.
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call void asm sideeffect "; $0", "r"(<2 x i32> %a)
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ret void
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}
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; CHECK-LABEL: test_inst_offset_function
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define void @test_inst_offset_function() {
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entry:
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; Occupy 4092 bytes of scratch, so the offset of the spill of %a just fits in
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; the instruction offset field.
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%alloca = alloca i8, i32 4092, align 4, addrspace(5)
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%buf = bitcast i8 addrspace(5)* %alloca to i32 addrspace(5)*
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%aptr = getelementptr i32, i32 addrspace(5)* %buf, i32 1
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; CHECK: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4092 ; 4-byte Folded Spill
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%a = load volatile i32, i32 addrspace(5)* %aptr
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; Force %a to spill.
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call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}" ()
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%outptr = getelementptr i32, i32 addrspace(5)* %buf, i32 1
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store volatile i32 %a, i32 addrspace(5)* %outptr
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ret void
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}
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; CHECK-LABEL: test_sgpr_offset_function
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define void @test_sgpr_offset_function() {
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entry:
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; Occupy 4096 bytes of scratch, so the offset of the spill of %a does not
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; fit in the instruction, and has to live in the SGPR offset.
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%alloca = alloca i8, i32 4096, align 4, addrspace(5)
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%buf = bitcast i8 addrspace(5)* %alloca to i32 addrspace(5)*
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%aptr = getelementptr i32, i32 addrspace(5)* %buf, i32 1
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; 0x40000 / 64 = 4096 (for wave64)
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; CHECK: s_add_u32 s4, s32, 0x40000
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; CHECK: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s4 ; 4-byte Folded Spill
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%a = load volatile i32, i32 addrspace(5)* %aptr
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; Force %a to spill
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call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}" ()
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%outptr = getelementptr i32, i32 addrspace(5)* %buf, i32 1
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store volatile i32 %a, i32 addrspace(5)* %outptr
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ret void
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}
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; CHECK-LABEL: test_sgpr_offset_subregs_function
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define void @test_sgpr_offset_subregs_function() {
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entry:
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; Occupy 4088 bytes of scratch, so that the spill of the last subreg of %a
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; still fits below offset 4096 (4088 + 8 - 4 = 4092), and can be placed in
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; the instruction offset field.
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%alloca = alloca i8, i32 4088, align 4, addrspace(5)
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%bufv1 = bitcast i8 addrspace(5)* %alloca to i32 addrspace(5)*
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%bufv2 = bitcast i8 addrspace(5)* %alloca to <2 x i32> addrspace(5)*
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; CHECK: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4088 ; 4-byte Folded Spill
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; CHECK: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4092 ; 4-byte Folded Spill
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%aptr = getelementptr <2 x i32>, <2 x i32> addrspace(5)* %bufv2, i32 1
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%a = load volatile <2 x i32>, <2 x i32> addrspace(5)* %aptr
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; Force %a to spill.
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call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}" ()
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; Ensure the alloca sticks around.
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%bptr = getelementptr i32, i32 addrspace(5)* %bufv1, i32 1
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%b = load volatile i32, i32 addrspace(5)* %bptr
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; Ensure the spill is of the full super-reg.
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call void asm sideeffect "; $0", "r"(<2 x i32> %a)
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ret void
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}
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; CHECK-LABEL: test_inst_offset_subregs_function
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define void @test_inst_offset_subregs_function() {
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entry:
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; Occupy 4092 bytes of scratch, so that the spill of the last subreg of %a
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; does not fit below offset 4096 (4092 + 8 - 4 = 4096), and has to live
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; in the SGPR offset.
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%alloca = alloca i8, i32 4092, align 4, addrspace(5)
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%bufv1 = bitcast i8 addrspace(5)* %alloca to i32 addrspace(5)*
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%bufv2 = bitcast i8 addrspace(5)* %alloca to <2 x i32> addrspace(5)*
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; 0x3ff00 / 64 = 4092 (for wave64)
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; CHECK: s_add_u32 s4, s32, 0x3ff00
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; CHECK: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s4 ; 4-byte Folded Spill
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; CHECK: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s4 offset:4 ; 4-byte Folded Spill
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%aptr = getelementptr <2 x i32>, <2 x i32> addrspace(5)* %bufv2, i32 1
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%a = load volatile <2 x i32>, <2 x i32> addrspace(5)* %aptr
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; Force %a to spill.
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call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}" ()
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; Ensure the alloca sticks around.
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%bptr = getelementptr i32, i32 addrspace(5)* %bufv1, i32 1
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%b = load volatile i32, i32 addrspace(5)* %bptr
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; Ensure the spill is of the full super-reg.
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call void asm sideeffect "; $0", "r"(<2 x i32> %a)
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind "amdgpu-num-sgpr"="17" "amdgpu-num-vgpr"="8" }
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attributes #2 = { nounwind "amdgpu-num-sgpr"="14" "amdgpu-num-vgpr"="8" }
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