Simon Pilgrim 081abbb164 [X86][SSE] Improve lowering of vXi64 multiplies ... As mentioned on PR30845, we were performing our vXi64 multiplication as: AloBlo = pmuludq(a, b); AloBhi = pmuludq(a, psrlqi(b, 32)); AhiBlo = pmuludq(psrlqi(a, 32), b); return AloBlo + psllqi(AloBhi, 32)+ psllqi(AhiBlo, 32); when we could avoid one of the upper shifts with: AloBlo = pmuludq(a, b); AloBhi = pmuludq(a, psrlqi(b, 32)); AhiBlo = pmuludq(psrlqi(a, 32), b); return AloBlo + psllqi(AloBhi + AhiBlo, 32); This matches the lowering on gcc/icc. Differential Revision: https://reviews.llvm.org/D27756 llvm-svn: 290267		2016-12-21 20:00:10 +00:00
..
AArch64	[AArch64] Guard Misaligned 128-bit store penalty by subtarget feature	2016-12-15 18:36:59 +00:00
AMDGPU	AMDGPU: Cost model for basic integer operations	2016-03-25 01:16:40 +00:00
ARM	[TTI/CostModel] Correct the way getGEPCost() calls isLegalAddressingMode()	2016-12-03 01:57:24 +00:00
PowerPC	[ppc] Correctly compute the cost of loading 32/64 bit memory into VSR	2016-12-03 00:41:43 +00:00
X86	[X86][SSE] Improve lowering of vXi64 multiplies	2016-12-21 20:00:10 +00:00
no_info.ll	Roll forward r243250	2015-07-26 19:10:03 +00:00