forked from OSchip/llvm-project
1177 lines
46 KiB
C++
1177 lines
46 KiB
C++
//===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.cpp - MIBuilder--*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the MachineIRBuidler class.
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/Analysis/MemoryLocation.h"
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#include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/IR/DebugInfo.h"
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using namespace llvm;
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void MachineIRBuilder::setMF(MachineFunction &MF) {
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State.MF = &MF;
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State.MBB = nullptr;
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State.MRI = &MF.getRegInfo();
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State.TII = MF.getSubtarget().getInstrInfo();
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State.DL = DebugLoc();
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State.II = MachineBasicBlock::iterator();
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State.Observer = nullptr;
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}
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//------------------------------------------------------------------------------
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// Build instruction variants.
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//------------------------------------------------------------------------------
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MachineInstrBuilder MachineIRBuilder::buildInstrNoInsert(unsigned Opcode) {
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MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode));
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return MIB;
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}
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MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) {
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getMBB().insert(getInsertPt(), MIB);
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recordInsertion(MIB);
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return MIB;
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}
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MachineInstrBuilder
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MachineIRBuilder::buildDirectDbgValue(Register Reg, const MDNode *Variable,
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const MDNode *Expr) {
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assert(isa<DILocalVariable>(Variable) && "not a variable");
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assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
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assert(
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cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
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"Expected inlined-at fields to agree");
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return insertInstr(BuildMI(getMF(), getDL(),
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getTII().get(TargetOpcode::DBG_VALUE),
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/*IsIndirect*/ false, Reg, Variable, Expr));
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}
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MachineInstrBuilder
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MachineIRBuilder::buildIndirectDbgValue(Register Reg, const MDNode *Variable,
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const MDNode *Expr) {
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assert(isa<DILocalVariable>(Variable) && "not a variable");
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assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
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assert(
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cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
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"Expected inlined-at fields to agree");
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return insertInstr(BuildMI(getMF(), getDL(),
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getTII().get(TargetOpcode::DBG_VALUE),
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/*IsIndirect*/ true, Reg, Variable, Expr));
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}
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MachineInstrBuilder MachineIRBuilder::buildFIDbgValue(int FI,
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const MDNode *Variable,
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const MDNode *Expr) {
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assert(isa<DILocalVariable>(Variable) && "not a variable");
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assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
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assert(
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cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
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"Expected inlined-at fields to agree");
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return buildInstr(TargetOpcode::DBG_VALUE)
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.addFrameIndex(FI)
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.addImm(0)
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.addMetadata(Variable)
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.addMetadata(Expr);
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}
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MachineInstrBuilder MachineIRBuilder::buildConstDbgValue(const Constant &C,
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const MDNode *Variable,
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const MDNode *Expr) {
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assert(isa<DILocalVariable>(Variable) && "not a variable");
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assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
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assert(
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cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
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"Expected inlined-at fields to agree");
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auto MIB = buildInstrNoInsert(TargetOpcode::DBG_VALUE);
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if (auto *CI = dyn_cast<ConstantInt>(&C)) {
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if (CI->getBitWidth() > 64)
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MIB.addCImm(CI);
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else
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MIB.addImm(CI->getZExtValue());
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} else if (auto *CFP = dyn_cast<ConstantFP>(&C)) {
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MIB.addFPImm(CFP);
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} else {
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// Insert $noreg if we didn't find a usable constant and had to drop it.
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MIB.addReg(Register());
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}
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MIB.addImm(0).addMetadata(Variable).addMetadata(Expr);
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return insertInstr(MIB);
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}
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MachineInstrBuilder MachineIRBuilder::buildDbgLabel(const MDNode *Label) {
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assert(isa<DILabel>(Label) && "not a label");
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assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(State.DL) &&
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"Expected inlined-at fields to agree");
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auto MIB = buildInstr(TargetOpcode::DBG_LABEL);
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return MIB.addMetadata(Label);
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}
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MachineInstrBuilder MachineIRBuilder::buildDynStackAlloc(const DstOp &Res,
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const SrcOp &Size,
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Align Alignment) {
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assert(Res.getLLTTy(*getMRI()).isPointer() && "expected ptr dst type");
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auto MIB = buildInstr(TargetOpcode::G_DYN_STACKALLOC);
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Res.addDefToMIB(*getMRI(), MIB);
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Size.addSrcToMIB(MIB);
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MIB.addImm(Alignment.value());
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return MIB;
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}
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MachineInstrBuilder MachineIRBuilder::buildFrameIndex(const DstOp &Res,
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int Idx) {
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assert(Res.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
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auto MIB = buildInstr(TargetOpcode::G_FRAME_INDEX);
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Res.addDefToMIB(*getMRI(), MIB);
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MIB.addFrameIndex(Idx);
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return MIB;
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}
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MachineInstrBuilder MachineIRBuilder::buildGlobalValue(const DstOp &Res,
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const GlobalValue *GV) {
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assert(Res.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
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assert(Res.getLLTTy(*getMRI()).getAddressSpace() ==
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GV->getType()->getAddressSpace() &&
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"address space mismatch");
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auto MIB = buildInstr(TargetOpcode::G_GLOBAL_VALUE);
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Res.addDefToMIB(*getMRI(), MIB);
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MIB.addGlobalAddress(GV);
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return MIB;
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}
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MachineInstrBuilder MachineIRBuilder::buildJumpTable(const LLT PtrTy,
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unsigned JTI) {
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return buildInstr(TargetOpcode::G_JUMP_TABLE, {PtrTy}, {})
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.addJumpTableIndex(JTI);
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}
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void MachineIRBuilder::validateBinaryOp(const LLT Res, const LLT Op0,
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const LLT Op1) {
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assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
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assert((Res == Op0 && Res == Op1) && "type mismatch");
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}
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void MachineIRBuilder::validateShiftOp(const LLT Res, const LLT Op0,
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const LLT Op1) {
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assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
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assert((Res == Op0) && "type mismatch");
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}
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MachineInstrBuilder MachineIRBuilder::buildPtrAdd(const DstOp &Res,
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const SrcOp &Op0,
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const SrcOp &Op1) {
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assert(Res.getLLTTy(*getMRI()).getScalarType().isPointer() &&
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Res.getLLTTy(*getMRI()) == Op0.getLLTTy(*getMRI()) && "type mismatch");
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assert(Op1.getLLTTy(*getMRI()).getScalarType().isScalar() && "invalid offset type");
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return buildInstr(TargetOpcode::G_PTR_ADD, {Res}, {Op0, Op1});
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}
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Optional<MachineInstrBuilder>
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MachineIRBuilder::materializePtrAdd(Register &Res, Register Op0,
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const LLT ValueTy, uint64_t Value) {
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assert(Res == 0 && "Res is a result argument");
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assert(ValueTy.isScalar() && "invalid offset type");
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if (Value == 0) {
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Res = Op0;
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return None;
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}
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Res = getMRI()->createGenericVirtualRegister(getMRI()->getType(Op0));
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auto Cst = buildConstant(ValueTy, Value);
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return buildPtrAdd(Res, Op0, Cst.getReg(0));
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}
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MachineInstrBuilder MachineIRBuilder::buildMaskLowPtrBits(const DstOp &Res,
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const SrcOp &Op0,
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uint32_t NumBits) {
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LLT PtrTy = Res.getLLTTy(*getMRI());
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LLT MaskTy = LLT::scalar(PtrTy.getSizeInBits());
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Register MaskReg = getMRI()->createGenericVirtualRegister(MaskTy);
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buildConstant(MaskReg, maskTrailingZeros<uint64_t>(NumBits));
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return buildPtrMask(Res, Op0, MaskReg);
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}
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MachineInstrBuilder MachineIRBuilder::buildBr(MachineBasicBlock &Dest) {
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return buildInstr(TargetOpcode::G_BR).addMBB(&Dest);
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}
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MachineInstrBuilder MachineIRBuilder::buildBrIndirect(Register Tgt) {
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assert(getMRI()->getType(Tgt).isPointer() && "invalid branch destination");
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return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt);
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}
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MachineInstrBuilder MachineIRBuilder::buildBrJT(Register TablePtr,
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unsigned JTI,
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Register IndexReg) {
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assert(getMRI()->getType(TablePtr).isPointer() &&
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"Table reg must be a pointer");
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return buildInstr(TargetOpcode::G_BRJT)
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.addUse(TablePtr)
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.addJumpTableIndex(JTI)
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.addUse(IndexReg);
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}
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MachineInstrBuilder MachineIRBuilder::buildCopy(const DstOp &Res,
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const SrcOp &Op) {
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return buildInstr(TargetOpcode::COPY, Res, Op);
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}
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MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
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const ConstantInt &Val) {
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LLT Ty = Res.getLLTTy(*getMRI());
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LLT EltTy = Ty.getScalarType();
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assert(EltTy.getScalarSizeInBits() == Val.getBitWidth() &&
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"creating constant with the wrong size");
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if (Ty.isVector()) {
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auto Const = buildInstr(TargetOpcode::G_CONSTANT)
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.addDef(getMRI()->createGenericVirtualRegister(EltTy))
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.addCImm(&Val);
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return buildSplatVector(Res, Const);
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}
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auto Const = buildInstr(TargetOpcode::G_CONSTANT);
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Const->setDebugLoc(DebugLoc());
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Res.addDefToMIB(*getMRI(), Const);
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Const.addCImm(&Val);
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return Const;
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}
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MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
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int64_t Val) {
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auto IntN = IntegerType::get(getMF().getFunction().getContext(),
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Res.getLLTTy(*getMRI()).getScalarSizeInBits());
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ConstantInt *CI = ConstantInt::get(IntN, Val, true);
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return buildConstant(Res, *CI);
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}
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MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res,
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const ConstantFP &Val) {
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LLT Ty = Res.getLLTTy(*getMRI());
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LLT EltTy = Ty.getScalarType();
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assert(APFloat::getSizeInBits(Val.getValueAPF().getSemantics())
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== EltTy.getSizeInBits() &&
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"creating fconstant with the wrong size");
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assert(!Ty.isPointer() && "invalid operand type");
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if (Ty.isVector()) {
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auto Const = buildInstr(TargetOpcode::G_FCONSTANT)
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.addDef(getMRI()->createGenericVirtualRegister(EltTy))
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.addFPImm(&Val);
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return buildSplatVector(Res, Const);
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}
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auto Const = buildInstr(TargetOpcode::G_FCONSTANT);
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Const->setDebugLoc(DebugLoc());
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Res.addDefToMIB(*getMRI(), Const);
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Const.addFPImm(&Val);
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return Const;
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}
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MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
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const APInt &Val) {
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ConstantInt *CI = ConstantInt::get(getMF().getFunction().getContext(), Val);
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return buildConstant(Res, *CI);
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}
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MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res,
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double Val) {
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LLT DstTy = Res.getLLTTy(*getMRI());
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auto &Ctx = getMF().getFunction().getContext();
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auto *CFP =
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ConstantFP::get(Ctx, getAPFloatFromSize(Val, DstTy.getScalarSizeInBits()));
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return buildFConstant(Res, *CFP);
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}
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MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res,
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const APFloat &Val) {
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auto &Ctx = getMF().getFunction().getContext();
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auto *CFP = ConstantFP::get(Ctx, Val);
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return buildFConstant(Res, *CFP);
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}
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MachineInstrBuilder MachineIRBuilder::buildBrCond(Register Tst,
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MachineBasicBlock &Dest) {
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assert(getMRI()->getType(Tst).isScalar() && "invalid operand type");
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return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest);
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}
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MachineInstrBuilder
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MachineIRBuilder::buildLoad(const DstOp &Dst, const SrcOp &Addr,
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MachinePointerInfo PtrInfo, Align Alignment,
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MachineMemOperand::Flags MMOFlags,
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const AAMDNodes &AAInfo) {
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MMOFlags |= MachineMemOperand::MOLoad;
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assert((MMOFlags & MachineMemOperand::MOStore) == 0);
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uint64_t Size = MemoryLocation::getSizeOrUnknown(
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TypeSize::Fixed(Dst.getLLTTy(*getMRI()).getSizeInBytes()));
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MachineMemOperand *MMO =
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getMF().getMachineMemOperand(PtrInfo, MMOFlags, Size, Alignment, AAInfo);
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return buildLoad(Dst, Addr, *MMO);
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}
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MachineInstrBuilder MachineIRBuilder::buildLoadInstr(unsigned Opcode,
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const DstOp &Res,
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const SrcOp &Addr,
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MachineMemOperand &MMO) {
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assert(Res.getLLTTy(*getMRI()).isValid() && "invalid operand type");
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assert(Addr.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
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auto MIB = buildInstr(Opcode);
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Res.addDefToMIB(*getMRI(), MIB);
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Addr.addSrcToMIB(MIB);
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MIB.addMemOperand(&MMO);
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return MIB;
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}
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MachineInstrBuilder MachineIRBuilder::buildLoadFromOffset(
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const DstOp &Dst, const SrcOp &BasePtr,
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MachineMemOperand &BaseMMO, int64_t Offset) {
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LLT LoadTy = Dst.getLLTTy(*getMRI());
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MachineMemOperand *OffsetMMO =
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getMF().getMachineMemOperand(&BaseMMO, Offset, LoadTy.getSizeInBytes());
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if (Offset == 0) // This may be a size or type changing load.
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return buildLoad(Dst, BasePtr, *OffsetMMO);
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LLT PtrTy = BasePtr.getLLTTy(*getMRI());
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LLT OffsetTy = LLT::scalar(PtrTy.getSizeInBits());
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auto ConstOffset = buildConstant(OffsetTy, Offset);
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auto Ptr = buildPtrAdd(PtrTy, BasePtr, ConstOffset);
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return buildLoad(Dst, Ptr, *OffsetMMO);
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}
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MachineInstrBuilder MachineIRBuilder::buildStore(const SrcOp &Val,
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const SrcOp &Addr,
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MachineMemOperand &MMO) {
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assert(Val.getLLTTy(*getMRI()).isValid() && "invalid operand type");
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assert(Addr.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
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auto MIB = buildInstr(TargetOpcode::G_STORE);
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Val.addSrcToMIB(MIB);
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Addr.addSrcToMIB(MIB);
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MIB.addMemOperand(&MMO);
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return MIB;
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}
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MachineInstrBuilder
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MachineIRBuilder::buildStore(const SrcOp &Val, const SrcOp &Addr,
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MachinePointerInfo PtrInfo, Align Alignment,
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MachineMemOperand::Flags MMOFlags,
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const AAMDNodes &AAInfo) {
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MMOFlags |= MachineMemOperand::MOStore;
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assert((MMOFlags & MachineMemOperand::MOLoad) == 0);
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uint64_t Size = MemoryLocation::getSizeOrUnknown(
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TypeSize::Fixed(Val.getLLTTy(*getMRI()).getSizeInBytes()));
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MachineMemOperand *MMO =
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getMF().getMachineMemOperand(PtrInfo, MMOFlags, Size, Alignment, AAInfo);
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return buildStore(Val, Addr, *MMO);
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}
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MachineInstrBuilder MachineIRBuilder::buildAnyExt(const DstOp &Res,
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const SrcOp &Op) {
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return buildInstr(TargetOpcode::G_ANYEXT, Res, Op);
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}
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MachineInstrBuilder MachineIRBuilder::buildSExt(const DstOp &Res,
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const SrcOp &Op) {
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return buildInstr(TargetOpcode::G_SEXT, Res, Op);
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}
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MachineInstrBuilder MachineIRBuilder::buildZExt(const DstOp &Res,
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const SrcOp &Op) {
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return buildInstr(TargetOpcode::G_ZEXT, Res, Op);
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}
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unsigned MachineIRBuilder::getBoolExtOp(bool IsVec, bool IsFP) const {
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const auto *TLI = getMF().getSubtarget().getTargetLowering();
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switch (TLI->getBooleanContents(IsVec, IsFP)) {
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case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
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return TargetOpcode::G_SEXT;
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case TargetLoweringBase::ZeroOrOneBooleanContent:
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return TargetOpcode::G_ZEXT;
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default:
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return TargetOpcode::G_ANYEXT;
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}
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}
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MachineInstrBuilder MachineIRBuilder::buildBoolExt(const DstOp &Res,
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const SrcOp &Op,
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bool IsFP) {
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unsigned ExtOp = getBoolExtOp(getMRI()->getType(Op.getReg()).isVector(), IsFP);
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return buildInstr(ExtOp, Res, Op);
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}
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MachineInstrBuilder MachineIRBuilder::buildExtOrTrunc(unsigned ExtOpc,
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const DstOp &Res,
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const SrcOp &Op) {
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assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc ||
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TargetOpcode::G_SEXT == ExtOpc) &&
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"Expecting Extending Opc");
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assert(Res.getLLTTy(*getMRI()).isScalar() ||
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Res.getLLTTy(*getMRI()).isVector());
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assert(Res.getLLTTy(*getMRI()).isScalar() ==
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Op.getLLTTy(*getMRI()).isScalar());
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unsigned Opcode = TargetOpcode::COPY;
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if (Res.getLLTTy(*getMRI()).getSizeInBits() >
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Op.getLLTTy(*getMRI()).getSizeInBits())
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Opcode = ExtOpc;
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else if (Res.getLLTTy(*getMRI()).getSizeInBits() <
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Op.getLLTTy(*getMRI()).getSizeInBits())
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Opcode = TargetOpcode::G_TRUNC;
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else
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assert(Res.getLLTTy(*getMRI()) == Op.getLLTTy(*getMRI()));
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return buildInstr(Opcode, Res, Op);
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}
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MachineInstrBuilder MachineIRBuilder::buildSExtOrTrunc(const DstOp &Res,
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const SrcOp &Op) {
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return buildExtOrTrunc(TargetOpcode::G_SEXT, Res, Op);
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}
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MachineInstrBuilder MachineIRBuilder::buildZExtOrTrunc(const DstOp &Res,
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const SrcOp &Op) {
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return buildExtOrTrunc(TargetOpcode::G_ZEXT, Res, Op);
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}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildAnyExtOrTrunc(const DstOp &Res,
|
|
const SrcOp &Op) {
|
|
return buildExtOrTrunc(TargetOpcode::G_ANYEXT, Res, Op);
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildCast(const DstOp &Dst,
|
|
const SrcOp &Src) {
|
|
LLT SrcTy = Src.getLLTTy(*getMRI());
|
|
LLT DstTy = Dst.getLLTTy(*getMRI());
|
|
if (SrcTy == DstTy)
|
|
return buildCopy(Dst, Src);
|
|
|
|
unsigned Opcode;
|
|
if (SrcTy.isPointer() && DstTy.isScalar())
|
|
Opcode = TargetOpcode::G_PTRTOINT;
|
|
else if (DstTy.isPointer() && SrcTy.isScalar())
|
|
Opcode = TargetOpcode::G_INTTOPTR;
|
|
else {
|
|
assert(!SrcTy.isPointer() && !DstTy.isPointer() && "n G_ADDRCAST yet");
|
|
Opcode = TargetOpcode::G_BITCAST;
|
|
}
|
|
|
|
return buildInstr(Opcode, Dst, Src);
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildExtract(const DstOp &Dst,
|
|
const SrcOp &Src,
|
|
uint64_t Index) {
|
|
LLT SrcTy = Src.getLLTTy(*getMRI());
|
|
LLT DstTy = Dst.getLLTTy(*getMRI());
|
|
|
|
#ifndef NDEBUG
|
|
assert(SrcTy.isValid() && "invalid operand type");
|
|
assert(DstTy.isValid() && "invalid operand type");
|
|
assert(Index + DstTy.getSizeInBits() <= SrcTy.getSizeInBits() &&
|
|
"extracting off end of register");
|
|
#endif
|
|
|
|
if (DstTy.getSizeInBits() == SrcTy.getSizeInBits()) {
|
|
assert(Index == 0 && "insertion past the end of a register");
|
|
return buildCast(Dst, Src);
|
|
}
|
|
|
|
auto Extract = buildInstr(TargetOpcode::G_EXTRACT);
|
|
Dst.addDefToMIB(*getMRI(), Extract);
|
|
Src.addSrcToMIB(Extract);
|
|
Extract.addImm(Index);
|
|
return Extract;
|
|
}
|
|
|
|
void MachineIRBuilder::buildSequence(Register Res, ArrayRef<Register> Ops,
|
|
ArrayRef<uint64_t> Indices) {
|
|
#ifndef NDEBUG
|
|
assert(Ops.size() == Indices.size() && "incompatible args");
|
|
assert(!Ops.empty() && "invalid trivial sequence");
|
|
assert(llvm::is_sorted(Indices) &&
|
|
"sequence offsets must be in ascending order");
|
|
|
|
assert(getMRI()->getType(Res).isValid() && "invalid operand type");
|
|
for (auto Op : Ops)
|
|
assert(getMRI()->getType(Op).isValid() && "invalid operand type");
|
|
#endif
|
|
|
|
LLT ResTy = getMRI()->getType(Res);
|
|
LLT OpTy = getMRI()->getType(Ops[0]);
|
|
unsigned OpSize = OpTy.getSizeInBits();
|
|
bool MaybeMerge = true;
|
|
for (unsigned i = 0; i < Ops.size(); ++i) {
|
|
if (getMRI()->getType(Ops[i]) != OpTy || Indices[i] != i * OpSize) {
|
|
MaybeMerge = false;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (MaybeMerge && Ops.size() * OpSize == ResTy.getSizeInBits()) {
|
|
buildMerge(Res, Ops);
|
|
return;
|
|
}
|
|
|
|
Register ResIn = getMRI()->createGenericVirtualRegister(ResTy);
|
|
buildUndef(ResIn);
|
|
|
|
for (unsigned i = 0; i < Ops.size(); ++i) {
|
|
Register ResOut = i + 1 == Ops.size()
|
|
? Res
|
|
: getMRI()->createGenericVirtualRegister(ResTy);
|
|
buildInsert(ResOut, ResIn, Ops[i], Indices[i]);
|
|
ResIn = ResOut;
|
|
}
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildUndef(const DstOp &Res) {
|
|
return buildInstr(TargetOpcode::G_IMPLICIT_DEF, {Res}, {});
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildMerge(const DstOp &Res,
|
|
ArrayRef<Register> Ops) {
|
|
// Unfortunately to convert from ArrayRef<LLT> to ArrayRef<SrcOp>,
|
|
// we need some temporary storage for the DstOp objects. Here we use a
|
|
// sufficiently large SmallVector to not go through the heap.
|
|
SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
|
|
assert(TmpVec.size() > 1);
|
|
return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, TmpVec);
|
|
}
|
|
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildMerge(const DstOp &Res,
|
|
std::initializer_list<SrcOp> Ops) {
|
|
assert(Ops.size() > 1);
|
|
return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, Ops);
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<LLT> Res,
|
|
const SrcOp &Op) {
|
|
// Unfortunately to convert from ArrayRef<LLT> to ArrayRef<DstOp>,
|
|
// we need some temporary storage for the DstOp objects. Here we use a
|
|
// sufficiently large SmallVector to not go through the heap.
|
|
SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
|
|
assert(TmpVec.size() > 1);
|
|
return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildUnmerge(LLT Res,
|
|
const SrcOp &Op) {
|
|
unsigned NumReg = Op.getLLTTy(*getMRI()).getSizeInBits() / Res.getSizeInBits();
|
|
SmallVector<Register, 8> TmpVec;
|
|
for (unsigned I = 0; I != NumReg; ++I)
|
|
TmpVec.push_back(getMRI()->createGenericVirtualRegister(Res));
|
|
return buildUnmerge(TmpVec, Op);
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<Register> Res,
|
|
const SrcOp &Op) {
|
|
// Unfortunately to convert from ArrayRef<Register> to ArrayRef<DstOp>,
|
|
// we need some temporary storage for the DstOp objects. Here we use a
|
|
// sufficiently large SmallVector to not go through the heap.
|
|
SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
|
|
assert(TmpVec.size() > 1);
|
|
return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildBuildVector(const DstOp &Res,
|
|
ArrayRef<Register> Ops) {
|
|
// Unfortunately to convert from ArrayRef<Register> to ArrayRef<SrcOp>,
|
|
// we need some temporary storage for the DstOp objects. Here we use a
|
|
// sufficiently large SmallVector to not go through the heap.
|
|
SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
|
|
return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildSplatVector(const DstOp &Res,
|
|
const SrcOp &Src) {
|
|
SmallVector<SrcOp, 8> TmpVec(Res.getLLTTy(*getMRI()).getNumElements(), Src);
|
|
return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
|
|
}
|
|
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildBuildVectorTrunc(const DstOp &Res,
|
|
ArrayRef<Register> Ops) {
|
|
// Unfortunately to convert from ArrayRef<Register> to ArrayRef<SrcOp>,
|
|
// we need some temporary storage for the DstOp objects. Here we use a
|
|
// sufficiently large SmallVector to not go through the heap.
|
|
SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
|
|
return buildInstr(TargetOpcode::G_BUILD_VECTOR_TRUNC, Res, TmpVec);
|
|
}
|
|
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildConcatVectors(const DstOp &Res, ArrayRef<Register> Ops) {
|
|
// Unfortunately to convert from ArrayRef<Register> to ArrayRef<SrcOp>,
|
|
// we need some temporary storage for the DstOp objects. Here we use a
|
|
// sufficiently large SmallVector to not go through the heap.
|
|
SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
|
|
return buildInstr(TargetOpcode::G_CONCAT_VECTORS, Res, TmpVec);
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildInsert(const DstOp &Res,
|
|
const SrcOp &Src,
|
|
const SrcOp &Op,
|
|
unsigned Index) {
|
|
assert(Index + Op.getLLTTy(*getMRI()).getSizeInBits() <=
|
|
Res.getLLTTy(*getMRI()).getSizeInBits() &&
|
|
"insertion past the end of a register");
|
|
|
|
if (Res.getLLTTy(*getMRI()).getSizeInBits() ==
|
|
Op.getLLTTy(*getMRI()).getSizeInBits()) {
|
|
return buildCast(Res, Op);
|
|
}
|
|
|
|
return buildInstr(TargetOpcode::G_INSERT, Res, {Src, Op, uint64_t(Index)});
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID,
|
|
ArrayRef<Register> ResultRegs,
|
|
bool HasSideEffects) {
|
|
auto MIB =
|
|
buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
|
|
: TargetOpcode::G_INTRINSIC);
|
|
for (unsigned ResultReg : ResultRegs)
|
|
MIB.addDef(ResultReg);
|
|
MIB.addIntrinsicID(ID);
|
|
return MIB;
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID,
|
|
ArrayRef<DstOp> Results,
|
|
bool HasSideEffects) {
|
|
auto MIB =
|
|
buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
|
|
: TargetOpcode::G_INTRINSIC);
|
|
for (DstOp Result : Results)
|
|
Result.addDefToMIB(*getMRI(), MIB);
|
|
MIB.addIntrinsicID(ID);
|
|
return MIB;
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildTrunc(const DstOp &Res,
|
|
const SrcOp &Op) {
|
|
return buildInstr(TargetOpcode::G_TRUNC, Res, Op);
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildFPTrunc(const DstOp &Res,
|
|
const SrcOp &Op,
|
|
Optional<unsigned> Flags) {
|
|
return buildInstr(TargetOpcode::G_FPTRUNC, Res, Op, Flags);
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildICmp(CmpInst::Predicate Pred,
|
|
const DstOp &Res,
|
|
const SrcOp &Op0,
|
|
const SrcOp &Op1) {
|
|
return buildInstr(TargetOpcode::G_ICMP, Res, {Pred, Op0, Op1});
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildFCmp(CmpInst::Predicate Pred,
|
|
const DstOp &Res,
|
|
const SrcOp &Op0,
|
|
const SrcOp &Op1,
|
|
Optional<unsigned> Flags) {
|
|
|
|
return buildInstr(TargetOpcode::G_FCMP, Res, {Pred, Op0, Op1}, Flags);
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildSelect(const DstOp &Res,
|
|
const SrcOp &Tst,
|
|
const SrcOp &Op0,
|
|
const SrcOp &Op1,
|
|
Optional<unsigned> Flags) {
|
|
|
|
return buildInstr(TargetOpcode::G_SELECT, {Res}, {Tst, Op0, Op1}, Flags);
|
|
}
|
|
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildInsertVectorElement(const DstOp &Res, const SrcOp &Val,
|
|
const SrcOp &Elt, const SrcOp &Idx) {
|
|
return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT, Res, {Val, Elt, Idx});
|
|
}
|
|
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildExtractVectorElement(const DstOp &Res, const SrcOp &Val,
|
|
const SrcOp &Idx) {
|
|
return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT, Res, {Val, Idx});
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildAtomicCmpXchgWithSuccess(
|
|
Register OldValRes, Register SuccessRes, Register Addr, Register CmpVal,
|
|
Register NewVal, MachineMemOperand &MMO) {
|
|
#ifndef NDEBUG
|
|
LLT OldValResTy = getMRI()->getType(OldValRes);
|
|
LLT SuccessResTy = getMRI()->getType(SuccessRes);
|
|
LLT AddrTy = getMRI()->getType(Addr);
|
|
LLT CmpValTy = getMRI()->getType(CmpVal);
|
|
LLT NewValTy = getMRI()->getType(NewVal);
|
|
assert(OldValResTy.isScalar() && "invalid operand type");
|
|
assert(SuccessResTy.isScalar() && "invalid operand type");
|
|
assert(AddrTy.isPointer() && "invalid operand type");
|
|
assert(CmpValTy.isValid() && "invalid operand type");
|
|
assert(NewValTy.isValid() && "invalid operand type");
|
|
assert(OldValResTy == CmpValTy && "type mismatch");
|
|
assert(OldValResTy == NewValTy && "type mismatch");
|
|
#endif
|
|
|
|
return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS)
|
|
.addDef(OldValRes)
|
|
.addDef(SuccessRes)
|
|
.addUse(Addr)
|
|
.addUse(CmpVal)
|
|
.addUse(NewVal)
|
|
.addMemOperand(&MMO);
|
|
}
|
|
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildAtomicCmpXchg(Register OldValRes, Register Addr,
|
|
Register CmpVal, Register NewVal,
|
|
MachineMemOperand &MMO) {
|
|
#ifndef NDEBUG
|
|
LLT OldValResTy = getMRI()->getType(OldValRes);
|
|
LLT AddrTy = getMRI()->getType(Addr);
|
|
LLT CmpValTy = getMRI()->getType(CmpVal);
|
|
LLT NewValTy = getMRI()->getType(NewVal);
|
|
assert(OldValResTy.isScalar() && "invalid operand type");
|
|
assert(AddrTy.isPointer() && "invalid operand type");
|
|
assert(CmpValTy.isValid() && "invalid operand type");
|
|
assert(NewValTy.isValid() && "invalid operand type");
|
|
assert(OldValResTy == CmpValTy && "type mismatch");
|
|
assert(OldValResTy == NewValTy && "type mismatch");
|
|
#endif
|
|
|
|
return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG)
|
|
.addDef(OldValRes)
|
|
.addUse(Addr)
|
|
.addUse(CmpVal)
|
|
.addUse(NewVal)
|
|
.addMemOperand(&MMO);
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildAtomicRMW(
|
|
unsigned Opcode, const DstOp &OldValRes,
|
|
const SrcOp &Addr, const SrcOp &Val,
|
|
MachineMemOperand &MMO) {
|
|
|
|
#ifndef NDEBUG
|
|
LLT OldValResTy = OldValRes.getLLTTy(*getMRI());
|
|
LLT AddrTy = Addr.getLLTTy(*getMRI());
|
|
LLT ValTy = Val.getLLTTy(*getMRI());
|
|
assert(OldValResTy.isScalar() && "invalid operand type");
|
|
assert(AddrTy.isPointer() && "invalid operand type");
|
|
assert(ValTy.isValid() && "invalid operand type");
|
|
assert(OldValResTy == ValTy && "type mismatch");
|
|
assert(MMO.isAtomic() && "not atomic mem operand");
|
|
#endif
|
|
|
|
auto MIB = buildInstr(Opcode);
|
|
OldValRes.addDefToMIB(*getMRI(), MIB);
|
|
Addr.addSrcToMIB(MIB);
|
|
Val.addSrcToMIB(MIB);
|
|
MIB.addMemOperand(&MMO);
|
|
return MIB;
|
|
}
|
|
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildAtomicRMWXchg(Register OldValRes, Register Addr,
|
|
Register Val, MachineMemOperand &MMO) {
|
|
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XCHG, OldValRes, Addr, Val,
|
|
MMO);
|
|
}
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildAtomicRMWAdd(Register OldValRes, Register Addr,
|
|
Register Val, MachineMemOperand &MMO) {
|
|
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_ADD, OldValRes, Addr, Val,
|
|
MMO);
|
|
}
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildAtomicRMWSub(Register OldValRes, Register Addr,
|
|
Register Val, MachineMemOperand &MMO) {
|
|
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_SUB, OldValRes, Addr, Val,
|
|
MMO);
|
|
}
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildAtomicRMWAnd(Register OldValRes, Register Addr,
|
|
Register Val, MachineMemOperand &MMO) {
|
|
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_AND, OldValRes, Addr, Val,
|
|
MMO);
|
|
}
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildAtomicRMWNand(Register OldValRes, Register Addr,
|
|
Register Val, MachineMemOperand &MMO) {
|
|
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_NAND, OldValRes, Addr, Val,
|
|
MMO);
|
|
}
|
|
MachineInstrBuilder MachineIRBuilder::buildAtomicRMWOr(Register OldValRes,
|
|
Register Addr,
|
|
Register Val,
|
|
MachineMemOperand &MMO) {
|
|
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_OR, OldValRes, Addr, Val,
|
|
MMO);
|
|
}
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildAtomicRMWXor(Register OldValRes, Register Addr,
|
|
Register Val, MachineMemOperand &MMO) {
|
|
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XOR, OldValRes, Addr, Val,
|
|
MMO);
|
|
}
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildAtomicRMWMax(Register OldValRes, Register Addr,
|
|
Register Val, MachineMemOperand &MMO) {
|
|
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MAX, OldValRes, Addr, Val,
|
|
MMO);
|
|
}
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildAtomicRMWMin(Register OldValRes, Register Addr,
|
|
Register Val, MachineMemOperand &MMO) {
|
|
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MIN, OldValRes, Addr, Val,
|
|
MMO);
|
|
}
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildAtomicRMWUmax(Register OldValRes, Register Addr,
|
|
Register Val, MachineMemOperand &MMO) {
|
|
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMAX, OldValRes, Addr, Val,
|
|
MMO);
|
|
}
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildAtomicRMWUmin(Register OldValRes, Register Addr,
|
|
Register Val, MachineMemOperand &MMO) {
|
|
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMIN, OldValRes, Addr, Val,
|
|
MMO);
|
|
}
|
|
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildAtomicRMWFAdd(
|
|
const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
|
|
MachineMemOperand &MMO) {
|
|
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_FADD, OldValRes, Addr, Val,
|
|
MMO);
|
|
}
|
|
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildAtomicRMWFSub(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
|
|
MachineMemOperand &MMO) {
|
|
return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_FSUB, OldValRes, Addr, Val,
|
|
MMO);
|
|
}
|
|
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildFence(unsigned Ordering, unsigned Scope) {
|
|
return buildInstr(TargetOpcode::G_FENCE)
|
|
.addImm(Ordering)
|
|
.addImm(Scope);
|
|
}
|
|
|
|
MachineInstrBuilder
|
|
MachineIRBuilder::buildBlockAddress(Register Res, const BlockAddress *BA) {
|
|
#ifndef NDEBUG
|
|
assert(getMRI()->getType(Res).isPointer() && "invalid res type");
|
|
#endif
|
|
|
|
return buildInstr(TargetOpcode::G_BLOCK_ADDR).addDef(Res).addBlockAddress(BA);
|
|
}
|
|
|
|
void MachineIRBuilder::validateTruncExt(const LLT DstTy, const LLT SrcTy,
|
|
bool IsExtend) {
|
|
#ifndef NDEBUG
|
|
if (DstTy.isVector()) {
|
|
assert(SrcTy.isVector() && "mismatched cast between vector and non-vector");
|
|
assert(SrcTy.getNumElements() == DstTy.getNumElements() &&
|
|
"different number of elements in a trunc/ext");
|
|
} else
|
|
assert(DstTy.isScalar() && SrcTy.isScalar() && "invalid extend/trunc");
|
|
|
|
if (IsExtend)
|
|
assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() &&
|
|
"invalid narrowing extend");
|
|
else
|
|
assert(DstTy.getSizeInBits() < SrcTy.getSizeInBits() &&
|
|
"invalid widening trunc");
|
|
#endif
|
|
}
|
|
|
|
void MachineIRBuilder::validateSelectOp(const LLT ResTy, const LLT TstTy,
|
|
const LLT Op0Ty, const LLT Op1Ty) {
|
|
#ifndef NDEBUG
|
|
assert((ResTy.isScalar() || ResTy.isVector() || ResTy.isPointer()) &&
|
|
"invalid operand type");
|
|
assert((ResTy == Op0Ty && ResTy == Op1Ty) && "type mismatch");
|
|
if (ResTy.isScalar() || ResTy.isPointer())
|
|
assert(TstTy.isScalar() && "type mismatch");
|
|
else
|
|
assert((TstTy.isScalar() ||
|
|
(TstTy.isVector() &&
|
|
TstTy.getNumElements() == Op0Ty.getNumElements())) &&
|
|
"type mismatch");
|
|
#endif
|
|
}
|
|
|
|
MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opc,
|
|
ArrayRef<DstOp> DstOps,
|
|
ArrayRef<SrcOp> SrcOps,
|
|
Optional<unsigned> Flags) {
|
|
switch (Opc) {
|
|
default:
|
|
break;
|
|
case TargetOpcode::G_SELECT: {
|
|
assert(DstOps.size() == 1 && "Invalid select");
|
|
assert(SrcOps.size() == 3 && "Invalid select");
|
|
validateSelectOp(
|
|
DstOps[0].getLLTTy(*getMRI()), SrcOps[0].getLLTTy(*getMRI()),
|
|
SrcOps[1].getLLTTy(*getMRI()), SrcOps[2].getLLTTy(*getMRI()));
|
|
break;
|
|
}
|
|
case TargetOpcode::G_ADD:
|
|
case TargetOpcode::G_AND:
|
|
case TargetOpcode::G_MUL:
|
|
case TargetOpcode::G_OR:
|
|
case TargetOpcode::G_SUB:
|
|
case TargetOpcode::G_XOR:
|
|
case TargetOpcode::G_UDIV:
|
|
case TargetOpcode::G_SDIV:
|
|
case TargetOpcode::G_UREM:
|
|
case TargetOpcode::G_SREM:
|
|
case TargetOpcode::G_SMIN:
|
|
case TargetOpcode::G_SMAX:
|
|
case TargetOpcode::G_UMIN:
|
|
case TargetOpcode::G_UMAX:
|
|
case TargetOpcode::G_UADDSAT:
|
|
case TargetOpcode::G_SADDSAT:
|
|
case TargetOpcode::G_USUBSAT:
|
|
case TargetOpcode::G_SSUBSAT: {
|
|
// All these are binary ops.
|
|
assert(DstOps.size() == 1 && "Invalid Dst");
|
|
assert(SrcOps.size() == 2 && "Invalid Srcs");
|
|
validateBinaryOp(DstOps[0].getLLTTy(*getMRI()),
|
|
SrcOps[0].getLLTTy(*getMRI()),
|
|
SrcOps[1].getLLTTy(*getMRI()));
|
|
break;
|
|
}
|
|
case TargetOpcode::G_SHL:
|
|
case TargetOpcode::G_ASHR:
|
|
case TargetOpcode::G_LSHR: {
|
|
assert(DstOps.size() == 1 && "Invalid Dst");
|
|
assert(SrcOps.size() == 2 && "Invalid Srcs");
|
|
validateShiftOp(DstOps[0].getLLTTy(*getMRI()),
|
|
SrcOps[0].getLLTTy(*getMRI()),
|
|
SrcOps[1].getLLTTy(*getMRI()));
|
|
break;
|
|
}
|
|
case TargetOpcode::G_SEXT:
|
|
case TargetOpcode::G_ZEXT:
|
|
case TargetOpcode::G_ANYEXT:
|
|
assert(DstOps.size() == 1 && "Invalid Dst");
|
|
assert(SrcOps.size() == 1 && "Invalid Srcs");
|
|
validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
|
|
SrcOps[0].getLLTTy(*getMRI()), true);
|
|
break;
|
|
case TargetOpcode::G_TRUNC:
|
|
case TargetOpcode::G_FPTRUNC: {
|
|
assert(DstOps.size() == 1 && "Invalid Dst");
|
|
assert(SrcOps.size() == 1 && "Invalid Srcs");
|
|
validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
|
|
SrcOps[0].getLLTTy(*getMRI()), false);
|
|
break;
|
|
}
|
|
case TargetOpcode::G_BITCAST: {
|
|
assert(DstOps.size() == 1 && "Invalid Dst");
|
|
assert(SrcOps.size() == 1 && "Invalid Srcs");
|
|
assert(DstOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
|
|
SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() && "invalid bitcast");
|
|
break;
|
|
}
|
|
case TargetOpcode::COPY:
|
|
assert(DstOps.size() == 1 && "Invalid Dst");
|
|
// If the caller wants to add a subreg source it has to be done separately
|
|
// so we may not have any SrcOps at this point yet.
|
|
break;
|
|
case TargetOpcode::G_FCMP:
|
|
case TargetOpcode::G_ICMP: {
|
|
assert(DstOps.size() == 1 && "Invalid Dst Operands");
|
|
assert(SrcOps.size() == 3 && "Invalid Src Operands");
|
|
// For F/ICMP, the first src operand is the predicate, followed by
|
|
// the two comparands.
|
|
assert(SrcOps[0].getSrcOpKind() == SrcOp::SrcType::Ty_Predicate &&
|
|
"Expecting predicate");
|
|
assert([&]() -> bool {
|
|
CmpInst::Predicate Pred = SrcOps[0].getPredicate();
|
|
return Opc == TargetOpcode::G_ICMP ? CmpInst::isIntPredicate(Pred)
|
|
: CmpInst::isFPPredicate(Pred);
|
|
}() && "Invalid predicate");
|
|
assert(SrcOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
|
|
"Type mismatch");
|
|
assert([&]() -> bool {
|
|
LLT Op0Ty = SrcOps[1].getLLTTy(*getMRI());
|
|
LLT DstTy = DstOps[0].getLLTTy(*getMRI());
|
|
if (Op0Ty.isScalar() || Op0Ty.isPointer())
|
|
return DstTy.isScalar();
|
|
else
|
|
return DstTy.isVector() &&
|
|
DstTy.getNumElements() == Op0Ty.getNumElements();
|
|
}() && "Type Mismatch");
|
|
break;
|
|
}
|
|
case TargetOpcode::G_UNMERGE_VALUES: {
|
|
assert(!DstOps.empty() && "Invalid trivial sequence");
|
|
assert(SrcOps.size() == 1 && "Invalid src for Unmerge");
|
|
assert(std::all_of(DstOps.begin(), DstOps.end(),
|
|
[&, this](const DstOp &Op) {
|
|
return Op.getLLTTy(*getMRI()) ==
|
|
DstOps[0].getLLTTy(*getMRI());
|
|
}) &&
|
|
"type mismatch in output list");
|
|
assert(DstOps.size() * DstOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
|
|
SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
|
|
"input operands do not cover output register");
|
|
break;
|
|
}
|
|
case TargetOpcode::G_MERGE_VALUES: {
|
|
assert(!SrcOps.empty() && "invalid trivial sequence");
|
|
assert(DstOps.size() == 1 && "Invalid Dst");
|
|
assert(std::all_of(SrcOps.begin(), SrcOps.end(),
|
|
[&, this](const SrcOp &Op) {
|
|
return Op.getLLTTy(*getMRI()) ==
|
|
SrcOps[0].getLLTTy(*getMRI());
|
|
}) &&
|
|
"type mismatch in input list");
|
|
assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
|
|
DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
|
|
"input operands do not cover output register");
|
|
if (SrcOps.size() == 1)
|
|
return buildCast(DstOps[0], SrcOps[0]);
|
|
if (DstOps[0].getLLTTy(*getMRI()).isVector()) {
|
|
if (SrcOps[0].getLLTTy(*getMRI()).isVector())
|
|
return buildInstr(TargetOpcode::G_CONCAT_VECTORS, DstOps, SrcOps);
|
|
return buildInstr(TargetOpcode::G_BUILD_VECTOR, DstOps, SrcOps);
|
|
}
|
|
break;
|
|
}
|
|
case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
|
|
assert(DstOps.size() == 1 && "Invalid Dst size");
|
|
assert(SrcOps.size() == 2 && "Invalid Src size");
|
|
assert(SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
|
|
assert((DstOps[0].getLLTTy(*getMRI()).isScalar() ||
|
|
DstOps[0].getLLTTy(*getMRI()).isPointer()) &&
|
|
"Invalid operand type");
|
|
assert(SrcOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand type");
|
|
assert(SrcOps[0].getLLTTy(*getMRI()).getElementType() ==
|
|
DstOps[0].getLLTTy(*getMRI()) &&
|
|
"Type mismatch");
|
|
break;
|
|
}
|
|
case TargetOpcode::G_INSERT_VECTOR_ELT: {
|
|
assert(DstOps.size() == 1 && "Invalid dst size");
|
|
assert(SrcOps.size() == 3 && "Invalid src size");
|
|
assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
|
|
SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
|
|
assert(DstOps[0].getLLTTy(*getMRI()).getElementType() ==
|
|
SrcOps[1].getLLTTy(*getMRI()) &&
|
|
"Type mismatch");
|
|
assert(SrcOps[2].getLLTTy(*getMRI()).isScalar() && "Invalid index");
|
|
assert(DstOps[0].getLLTTy(*getMRI()).getNumElements() ==
|
|
SrcOps[0].getLLTTy(*getMRI()).getNumElements() &&
|
|
"Type mismatch");
|
|
break;
|
|
}
|
|
case TargetOpcode::G_BUILD_VECTOR: {
|
|
assert((!SrcOps.empty() || SrcOps.size() < 2) &&
|
|
"Must have at least 2 operands");
|
|
assert(DstOps.size() == 1 && "Invalid DstOps");
|
|
assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
|
|
"Res type must be a vector");
|
|
assert(std::all_of(SrcOps.begin(), SrcOps.end(),
|
|
[&, this](const SrcOp &Op) {
|
|
return Op.getLLTTy(*getMRI()) ==
|
|
SrcOps[0].getLLTTy(*getMRI());
|
|
}) &&
|
|
"type mismatch in input list");
|
|
assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
|
|
DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
|
|
"input scalars do not exactly cover the output vector register");
|
|
break;
|
|
}
|
|
case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
|
|
assert((!SrcOps.empty() || SrcOps.size() < 2) &&
|
|
"Must have at least 2 operands");
|
|
assert(DstOps.size() == 1 && "Invalid DstOps");
|
|
assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
|
|
"Res type must be a vector");
|
|
assert(std::all_of(SrcOps.begin(), SrcOps.end(),
|
|
[&, this](const SrcOp &Op) {
|
|
return Op.getLLTTy(*getMRI()) ==
|
|
SrcOps[0].getLLTTy(*getMRI());
|
|
}) &&
|
|
"type mismatch in input list");
|
|
if (SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
|
|
DstOps[0].getLLTTy(*getMRI()).getElementType().getSizeInBits())
|
|
return buildInstr(TargetOpcode::G_BUILD_VECTOR, DstOps, SrcOps);
|
|
break;
|
|
}
|
|
case TargetOpcode::G_CONCAT_VECTORS: {
|
|
assert(DstOps.size() == 1 && "Invalid DstOps");
|
|
assert((!SrcOps.empty() || SrcOps.size() < 2) &&
|
|
"Must have at least 2 operands");
|
|
assert(std::all_of(SrcOps.begin(), SrcOps.end(),
|
|
[&, this](const SrcOp &Op) {
|
|
return (Op.getLLTTy(*getMRI()).isVector() &&
|
|
Op.getLLTTy(*getMRI()) ==
|
|
SrcOps[0].getLLTTy(*getMRI()));
|
|
}) &&
|
|
"type mismatch in input list");
|
|
assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
|
|
DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
|
|
"input vectors do not exactly cover the output vector register");
|
|
break;
|
|
}
|
|
case TargetOpcode::G_UADDE: {
|
|
assert(DstOps.size() == 2 && "Invalid no of dst operands");
|
|
assert(SrcOps.size() == 3 && "Invalid no of src operands");
|
|
assert(DstOps[0].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
|
|
assert((DstOps[0].getLLTTy(*getMRI()) == SrcOps[0].getLLTTy(*getMRI())) &&
|
|
(DstOps[0].getLLTTy(*getMRI()) == SrcOps[1].getLLTTy(*getMRI())) &&
|
|
"Invalid operand");
|
|
assert(DstOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
|
|
assert(DstOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
|
|
"type mismatch");
|
|
break;
|
|
}
|
|
}
|
|
|
|
auto MIB = buildInstr(Opc);
|
|
for (const DstOp &Op : DstOps)
|
|
Op.addDefToMIB(*getMRI(), MIB);
|
|
for (const SrcOp &Op : SrcOps)
|
|
Op.addSrcToMIB(MIB);
|
|
if (Flags)
|
|
MIB->setFlags(*Flags);
|
|
return MIB;
|
|
}
|