forked from OSchip/llvm-project
181 lines
5.7 KiB
LLVM
181 lines
5.7 KiB
LLVM
; RUN: llc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s
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; RUN: llc -mtriple=x86_64-unknown-unknown -O0 < %s | FileCheck %s -check-prefix=CHECK0
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%struct.interrupt_frame = type { i64, i64, i64, i64, i64 }
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@sink_address = global i64* null
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@sink_i32 = global i64 0
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; Spills rax, putting original esp at +8.
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; No stack adjustment if declared with no error code
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define x86_intrcc void @test_isr_no_ecode(%struct.interrupt_frame* %frame) {
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; CHECK-LABEL: test_isr_no_ecode:
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; CHECK: pushq %rax
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; CHECK: movq 24(%rsp), %rax
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; CHECK: popq %rax
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; CHECK: iretq
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; CHECK0-LABEL: test_isr_no_ecode:
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; CHECK0: pushq %rax
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; CHECK0: leaq 8(%rsp), %rax
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; CHECK0: movq 16(%rax), %rax
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; CHECK0: popq %rax
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; CHECK0: iretq
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%pflags = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %frame, i32 0, i32 2
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%flags = load i64, i64* %pflags, align 4
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call void asm sideeffect "", "r"(i64 %flags)
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ret void
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}
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; Spills rax and rcx, putting original rsp at +16. Stack is adjusted up another 8 bytes
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; before return, popping the error code.
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define x86_intrcc void @test_isr_ecode(%struct.interrupt_frame* %frame, i64 %ecode) {
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; CHECK-LABEL: test_isr_ecode
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; CHECK: pushq %rax
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; CHECK: pushq %rax
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; CHECK: pushq %rcx
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; CHECK: movq 24(%rsp), %rax
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; CHECK: movq 48(%rsp), %rcx
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; CHECK: popq %rcx
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; CHECK: popq %rax
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; CHECK: addq $16, %rsp
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; CHECK: iretq
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; CHECK0-LABEL: test_isr_ecode
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; CHECK0: pushq %rax
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; CHECK0: pushq %rax
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; CHECK0: pushq %rcx
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; CHECK0: movq 24(%rsp), %rax
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; CHECK0: leaq 32(%rsp), %rcx
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; CHECK0: movq 16(%rcx), %rcx
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; CHECK0: popq %rcx
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; CHECK0: popq %rax
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; CHECK0: addq $16, %rsp
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; CHECK0: iretq
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%pflags = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %frame, i32 0, i32 2
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%flags = load i64, i64* %pflags, align 4
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call void asm sideeffect "", "r,r"(i64 %flags, i64 %ecode)
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ret void
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}
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; All clobbered registers must be saved
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define x86_intrcc void @test_isr_clobbers(%struct.interrupt_frame* %frame, i64 %ecode) {
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call void asm sideeffect "", "~{rax},~{rbx},~{rbp},~{r11},~{xmm0}"()
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; CHECK-LABEL: test_isr_clobbers
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; CHECK: pushq %rax
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; CHECK: pushq %rbp
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; CHECK: pushq %r11
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; CHECK: pushq %rbx
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; CHECK: movaps %xmm0
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; CHECK: movaps {{.*}}, %xmm0
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; CHECK: popq %rbx
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; CHECK: popq %r11
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; CHECK: popq %rbp
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; CHECK: popq %rax
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; CHECK: addq $16, %rsp
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; CHECK: iretq
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; CHECK0-LABEL: test_isr_clobbers
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; CHECK0: pushq %rax
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; CHECK0: pushq %rbp
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; CHECK0: pushq %r11
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; CHECK0: pushq %rbx
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; CHECK0: movaps %xmm0
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; CHECK0: movaps {{.*}}, %xmm0
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; CHECK0: popq %rbx
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; CHECK0: popq %r11
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; CHECK0: popq %rbp
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; CHECK0: popq %rax
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; CHECK0: addq $16, %rsp
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; CHECK0: iretq
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ret void
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}
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@f80 = common global x86_fp80 0xK00000000000000000000, align 4
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; Test that the presence of x87 does not crash the FP stackifier
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define x86_intrcc void @test_isr_x87(%struct.interrupt_frame* %frame) {
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; CHECK-LABEL: test_isr_x87
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; CHECK-DAG: fldt f80
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; CHECK-DAG: fld1
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; CHECK: faddp
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; CHECK-NEXT: fstpt f80
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; CHECK-NEXT: iretq
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entry:
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%ld = load x86_fp80, x86_fp80* @f80, align 4
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%add = fadd x86_fp80 %ld, 0xK3FFF8000000000000000
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store x86_fp80 %add, x86_fp80* @f80, align 4
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ret void
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}
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; Use a frame pointer to check the offsets. No return address, arguments start
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; at RBP+4.
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define dso_local x86_intrcc void @test_fp_1(%struct.interrupt_frame* %p) #0 {
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; CHECK-LABEL: test_fp_1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushq %rbp
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; CHECK-NEXT: movq %rsp, %rbp
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; CHECK: cld
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; CHECK-DAG: leaq 8(%rbp), %[[R1:[^ ]*]]
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; CHECK-DAG: leaq 40(%rbp), %[[R2:[^ ]*]]
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; CHECK: movq %[[R1]], sink_address
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; CHECK: movq %[[R2]], sink_address
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; CHECK: popq %rbp
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; CHECK: iretq
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entry:
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%arrayidx = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %p, i64 0, i32 0
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%arrayidx2 = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %p, i64 0, i32 4
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store volatile i64* %arrayidx, i64** @sink_address
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store volatile i64* %arrayidx2, i64** @sink_address
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ret void
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}
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; The error code is between RBP and the interrupt_frame.
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define dso_local x86_intrcc void @test_fp_2(%struct.interrupt_frame* %p, i64 %err) #0 {
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; CHECK-LABEL: test_fp_2:
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; CHECK: # %bb.0: # %entry
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; This RAX push is just to align the stack.
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; CHECK-NEXT: pushq %rax
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; CHECK-NEXT: pushq %rbp
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; CHECK-NEXT: movq %rsp, %rbp
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; CHECK: cld
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; CHECK-DAG: movq 16(%rbp), %[[R3:[^ ]*]]
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; CHECK-DAG: leaq 24(%rbp), %[[R1:[^ ]*]]
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; CHECK-DAG: leaq 56(%rbp), %[[R2:[^ ]*]]
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; CHECK: movq %[[R1]], sink_address(%rip)
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; CHECK: movq %[[R2]], sink_address(%rip)
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; CHECK: movq %[[R3]], sink_i32(%rip)
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; CHECK: popq %rbp
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; Pop off both the error code and the 8 byte alignment adjustment from the
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; prologue.
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; CHECK: addq $16, %rsp
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; CHECK: iretq
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entry:
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%arrayidx = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %p, i64 0, i32 0
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%arrayidx2 = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %p, i64 0, i32 4
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store volatile i64* %arrayidx, i64** @sink_address
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store volatile i64* %arrayidx2, i64** @sink_address
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store volatile i64 %err, i64* @sink_i32
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ret void
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}
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; Test argument copy elision when copied to a local alloca.
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define x86_intrcc void @test_copy_elide(%struct.interrupt_frame* %frame, i64 %err) #0 {
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; CHECK-LABEL: test_copy_elide:
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; CHECK: # %bb.0: # %entry
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; This RAX push is just to align the stack.
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; CHECK-NEXT: pushq %rax
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; CHECK-NEXT: pushq %rbp
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; CHECK-NEXT: movq %rsp, %rbp
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; CHECK: cld
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; CHECK: leaq 16(%rbp), %[[R1:[^ ]*]]
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; CHECK: movq %[[R1]], sink_address(%rip)
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entry:
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%err.addr = alloca i64, align 4
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store i64 %err, i64* %err.addr, align 4
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store volatile i64* %err.addr, i64** @sink_address
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ret void
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}
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attributes #0 = { nounwind "frame-pointer"="all" }
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