forked from OSchip/llvm-project
196 lines
5.4 KiB
LLVM
196 lines
5.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
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; The fundamental problem: an add separated from other arithmetic by a sign or
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; zero extension can't be combined with the later instructions. However, if the
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; first add is 'nsw' or 'nuw' respectively, then we can promote the extension
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; ahead of that add to allow optimizations.
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define i64 @add_nsw_consts(i32 %i) {
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; CHECK-LABEL: add_nsw_consts:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movslq %edi, %rax
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; CHECK-NEXT: addq $12, %rax
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; CHECK-NEXT: retq
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%add = add nsw i32 %i, 5
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%ext = sext i32 %add to i64
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%idx = add i64 %ext, 7
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ret i64 %idx
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}
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; An x86 bonus: If we promote the sext ahead of the 'add nsw',
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; we allow LEA formation and eliminate an add instruction.
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define i64 @add_nsw_sext_add(i32 %i, i64 %x) {
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; CHECK-LABEL: add_nsw_sext_add:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movslq %edi, %rax
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; CHECK-NEXT: leaq 5(%rax,%rsi), %rax
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; CHECK-NEXT: retq
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%add = add nsw i32 %i, 5
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%ext = sext i32 %add to i64
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%idx = add i64 %x, %ext
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ret i64 %idx
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}
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; Throw in a scale (left shift) because an LEA can do that too.
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; Use a negative constant (LEA displacement) to verify that's handled correctly.
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define i64 @add_nsw_sext_lsh_add(i32 %i, i64 %x) {
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; CHECK-LABEL: add_nsw_sext_lsh_add:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movslq %edi, %rax
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; CHECK-NEXT: leaq -40(%rsi,%rax,8), %rax
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; CHECK-NEXT: retq
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%add = add nsw i32 %i, -5
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%ext = sext i32 %add to i64
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%shl = shl i64 %ext, 3
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%idx = add i64 %x, %shl
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ret i64 %idx
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}
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; Don't promote the sext if it has no users. The wider add instruction needs an
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; extra byte to encode.
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define i64 @add_nsw_sext(i32 %i, i64 %x) {
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; CHECK-LABEL: add_nsw_sext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addl $5, %edi
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; CHECK-NEXT: movslq %edi, %rax
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; CHECK-NEXT: retq
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%add = add nsw i32 %i, 5
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%ext = sext i32 %add to i64
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ret i64 %ext
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}
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; The typical use case: a 64-bit system where an 'int' is used as an index into an array.
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define i8* @gep8(i32 %i, i8* %x) {
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; CHECK-LABEL: gep8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movslq %edi, %rax
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; CHECK-NEXT: leaq 5(%rax,%rsi), %rax
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; CHECK-NEXT: retq
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%add = add nsw i32 %i, 5
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%ext = sext i32 %add to i64
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%idx = getelementptr i8, i8* %x, i64 %ext
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ret i8* %idx
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}
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define i16* @gep16(i32 %i, i16* %x) {
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; CHECK-LABEL: gep16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movslq %edi, %rax
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; CHECK-NEXT: leaq -10(%rsi,%rax,2), %rax
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; CHECK-NEXT: retq
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%add = add nsw i32 %i, -5
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%ext = sext i32 %add to i64
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%idx = getelementptr i16, i16* %x, i64 %ext
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ret i16* %idx
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}
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define i32* @gep32(i32 %i, i32* %x) {
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; CHECK-LABEL: gep32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movslq %edi, %rax
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; CHECK-NEXT: leaq 20(%rsi,%rax,4), %rax
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; CHECK-NEXT: retq
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%add = add nsw i32 %i, 5
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%ext = sext i32 %add to i64
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%idx = getelementptr i32, i32* %x, i64 %ext
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ret i32* %idx
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}
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define i64* @gep64(i32 %i, i64* %x) {
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; CHECK-LABEL: gep64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movslq %edi, %rax
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; CHECK-NEXT: leaq -40(%rsi,%rax,8), %rax
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; CHECK-NEXT: retq
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%add = add nsw i32 %i, -5
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%ext = sext i32 %add to i64
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%idx = getelementptr i64, i64* %x, i64 %ext
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ret i64* %idx
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}
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; LEA can't scale by 16, but the adds can still be combined into an LEA.
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define i128* @gep128(i32 %i, i128* %x) {
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; CHECK-LABEL: gep128:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movslq %edi, %rax
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; CHECK-NEXT: shlq $4, %rax
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; CHECK-NEXT: leaq 80(%rax,%rsi), %rax
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; CHECK-NEXT: retq
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%add = add nsw i32 %i, 5
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%ext = sext i32 %add to i64
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%idx = getelementptr i128, i128* %x, i64 %ext
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ret i128* %idx
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}
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; A bigger win can be achieved when there is more than one use of the
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; sign extended value. In this case, we can eliminate sign extension
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; instructions plus use more efficient addressing modes for memory ops.
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define void @PR20134(i32* %a, i32 %i) {
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; CHECK-LABEL: PR20134:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movslq %esi, %rax
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; CHECK-NEXT: movl 4(%rdi,%rax,4), %ecx
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; CHECK-NEXT: addl 8(%rdi,%rax,4), %ecx
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; CHECK-NEXT: movl %ecx, (%rdi,%rax,4)
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; CHECK-NEXT: retq
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%add1 = add nsw i32 %i, 1
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%idx1 = sext i32 %add1 to i64
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%gep1 = getelementptr i32, i32* %a, i64 %idx1
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%load1 = load i32, i32* %gep1, align 4
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%add2 = add nsw i32 %i, 2
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%idx2 = sext i32 %add2 to i64
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%gep2 = getelementptr i32, i32* %a, i64 %idx2
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%load2 = load i32, i32* %gep2, align 4
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%add3 = add i32 %load1, %load2
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%idx3 = sext i32 %i to i64
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%gep3 = getelementptr i32, i32* %a, i64 %idx3
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store i32 %add3, i32* %gep3, align 4
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ret void
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}
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; The same as @PR20134 but sign extension is replaced with zero extension
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define void @PR20134_zext(i32* %a, i32 %i) {
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; CHECK-LABEL: PR20134_zext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: movl 4(%rdi,%rax,4), %ecx
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; CHECK-NEXT: addl 8(%rdi,%rax,4), %ecx
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; CHECK-NEXT: movl %ecx, (%rdi,%rax,4)
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; CHECK-NEXT: retq
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%add1 = add nuw i32 %i, 1
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%idx1 = zext i32 %add1 to i64
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%gep1 = getelementptr i32, i32* %a, i64 %idx1
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%load1 = load i32, i32* %gep1, align 4
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%add2 = add nuw i32 %i, 2
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%idx2 = zext i32 %add2 to i64
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%gep2 = getelementptr i32, i32* %a, i64 %idx2
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%load2 = load i32, i32* %gep2, align 4
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%add3 = add i32 %load1, %load2
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%idx3 = zext i32 %i to i64
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%gep3 = getelementptr i32, i32* %a, i64 %idx3
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store i32 %add3, i32* %gep3, align 4
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ret void
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}
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