forked from OSchip/llvm-project
168 lines
5.5 KiB
LLVM
168 lines
5.5 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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@d = external global <16 x i32>
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@c = external global <32 x i32>
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; CHECK-LABEL: test1:
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; CHECK: v{{[0-9]+}}.b = vpacke(v{{[0-9]+}}.h,v{{[0-9]+}}.h)
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define void @test1(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = tail call <16 x i32> @llvm.hexagon.V6.vpackeb(<16 x i32> %a, <16 x i32> %b)
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store <16 x i32> %0, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test2:
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; CHECK: v{{[0-9]+}}.h = vpacke(v{{[0-9]+}}.w,v{{[0-9]+}}.w)
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define void @test2(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = tail call <16 x i32> @llvm.hexagon.V6.vpackeh(<16 x i32> %a, <16 x i32> %b)
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store <16 x i32> %0, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test3:
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; CHECK: v{{[0-9]+}}.ub = vpack(v{{[0-9]+}}.h,v{{[0-9]+}}.h):sat
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define void @test3(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = tail call <16 x i32> @llvm.hexagon.V6.vpackhub.sat(<16 x i32> %a, <16 x i32> %b)
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store <16 x i32> %0, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test4:
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; CHECK: v{{[0-9]+}}.b = vpack(v{{[0-9]+}}.h,v{{[0-9]+}}.h):sat
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define void @test4(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = tail call <16 x i32> @llvm.hexagon.V6.vpackhb.sat(<16 x i32> %a, <16 x i32> %b)
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store <16 x i32> %0, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test5:
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; CHECK: v{{[0-9]+}}.uh = vpack(v{{[0-9]+}}.w,v{{[0-9]+}}.w):sat
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define void @test5(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = tail call <16 x i32> @llvm.hexagon.V6.vpackwuh.sat(<16 x i32> %a, <16 x i32> %b)
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store <16 x i32> %0, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test6:
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; CHECK: v{{[0-9]+}}.h = vpack(v{{[0-9]+}}.w,v{{[0-9]+}}.w):sat
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define void @test6(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = tail call <16 x i32> @llvm.hexagon.V6.vpackwh.sat(<16 x i32> %a, <16 x i32> %b)
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store <16 x i32> %0, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test7:
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; CHECK: v{{[0-9]+}}.b = vpacko(v{{[0-9]+}}.h,v{{[0-9]+}}.h)
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define void @test7(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = tail call <16 x i32> @llvm.hexagon.V6.vpackob(<16 x i32> %a, <16 x i32> %b)
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store <16 x i32> %0, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test8:
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; CHECK: v{{[0-9]+}}.h = vpacko(v{{[0-9]+}}.w,v{{[0-9]+}}.w)
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define void @test8(<16 x i32> %a, <16 x i32> %b) #0 {
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entry:
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%0 = tail call <16 x i32> @llvm.hexagon.V6.vpackoh(<16 x i32> %a, <16 x i32> %b)
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store <16 x i32> %0, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test9:
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; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uh = vunpack(v{{[0-9]+}}.ub)
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define void @test9(<16 x i32> %a) #0 {
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entry:
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%0 = tail call <32 x i32> @llvm.hexagon.V6.vunpackub(<16 x i32> %a)
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store <32 x i32> %0, <32 x i32>* @c, align 128
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ret void
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}
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; CHECK-LABEL: test10:
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; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uw = vunpack(v{{[0-9]+}}.uh)
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define void @test10(<16 x i32> %a) #0 {
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entry:
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%0 = tail call <32 x i32> @llvm.hexagon.V6.vunpackuh(<16 x i32> %a)
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store <32 x i32> %0, <32 x i32>* @c, align 128
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ret void
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}
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; CHECK-LABEL: test11:
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; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h = vunpack(v{{[0-9]+}}.b)
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define void @test11(<16 x i32> %a) #0 {
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entry:
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%0 = tail call <32 x i32> @llvm.hexagon.V6.vunpackb(<16 x i32> %a)
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store <32 x i32> %0, <32 x i32>* @c, align 128
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ret void
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}
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; CHECK-LABEL: test12:
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; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w = vunpack(v{{[0-9]+}}.h)
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define void @test12(<16 x i32> %a) #0 {
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entry:
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%0 = tail call <32 x i32> @llvm.hexagon.V6.vunpackh(<16 x i32> %a)
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store <32 x i32> %0, <32 x i32>* @c, align 128
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ret void
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}
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; CHECK-LABEL: test13:
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; CHECK: v{{[0-9]+}}.h = vdeal(v{{[0-9]+}}.h)
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define void @test13(<16 x i32> %a) #0 {
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entry:
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%0 = tail call <16 x i32> @llvm.hexagon.V6.vdealh(<16 x i32> %a)
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store <16 x i32> %0, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test14:
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; CHECK: v{{[0-9]+}}.b = vdeal(v{{[0-9]+}}.b)
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define void @test14(<16 x i32> %a) #0 {
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entry:
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%0 = tail call <16 x i32> @llvm.hexagon.V6.vdealb(<16 x i32> %a)
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store <16 x i32> %0, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test15:
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; CHECK: v{{[0-9]+}}.h = vshuff(v{{[0-9]+}}.h)
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define void @test15(<16 x i32> %a) #0 {
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entry:
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%0 = tail call <16 x i32> @llvm.hexagon.V6.vshuffh(<16 x i32> %a)
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store <16 x i32> %0, <16 x i32>* @d, align 64
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ret void
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}
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; CHECK-LABEL: test16:
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; CHECK: v{{[0-9]+}}.b = vshuff(v{{[0-9]+}}.b)
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define void @test16(<16 x i32> %a) #0 {
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entry:
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%0 = tail call <16 x i32> @llvm.hexagon.V6.vshuffb(<16 x i32> %a)
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store <16 x i32> %0, <16 x i32>* @d, align 64
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ret void
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}
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declare <16 x i32> @llvm.hexagon.V6.vpackeb(<16 x i32>, <16 x i32>) #0
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declare <16 x i32> @llvm.hexagon.V6.vpackeh(<16 x i32>, <16 x i32>) #0
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declare <16 x i32> @llvm.hexagon.V6.vpackhub.sat(<16 x i32>, <16 x i32>) #0
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declare <16 x i32> @llvm.hexagon.V6.vpackhb.sat(<16 x i32>, <16 x i32>) #0
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declare <16 x i32> @llvm.hexagon.V6.vpackwuh.sat(<16 x i32>, <16 x i32>) #0
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declare <16 x i32> @llvm.hexagon.V6.vpackwh.sat(<16 x i32>, <16 x i32>) #0
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declare <16 x i32> @llvm.hexagon.V6.vpackob(<16 x i32>, <16 x i32>) #0
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declare <16 x i32> @llvm.hexagon.V6.vpackoh(<16 x i32>, <16 x i32>) #0
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declare <32 x i32> @llvm.hexagon.V6.vunpackub(<16 x i32>) #0
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declare <32 x i32> @llvm.hexagon.V6.vunpackuh(<16 x i32>) #0
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declare <32 x i32> @llvm.hexagon.V6.vunpackb(<16 x i32>) #0
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declare <32 x i32> @llvm.hexagon.V6.vunpackh(<16 x i32>) #0
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declare <16 x i32> @llvm.hexagon.V6.vdealh(<16 x i32>) #0
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declare <16 x i32> @llvm.hexagon.V6.vdealb(<16 x i32>) #0
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declare <16 x i32> @llvm.hexagon.V6.vshuffh(<16 x i32>) #0
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declare <16 x i32> @llvm.hexagon.V6.vshuffb(<16 x i32>) #0
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attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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