llvm-project/llvm/test/CodeGen/Hexagon/expand-condsets-phys-reg.mir

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# RUN: llc -march=hexagon -run-pass expand-condsets %s -o - | FileCheck %s
# REQUIRES: asserts
# The physical register as an operand to C2_mux caused a crash.
# Check that this compiles successfully and that the mux is expanded.
# CHECK: %2:intregs = A2_tfrt %1, $r31
# CHECK: %2:intregs = A2_tfrf killed %1, killed %0, implicit %2(tied-def 0)
name: fred
tracksRegLiveness: true
body: |
bb.0:
successors: %bb.1, %bb.2
liveins: $r0
%0:intregs = A2_tfrsi 0 ;; Multiple defs to ensure IsSSA = false
%0:intregs = L2_loadri_io $r0, 0
%1:predregs = C2_cmpgti %0, 10
%2:intregs = C2_mux %1, $r31, %0
%3:predregs = C2_cmpeqi %2, 0
J2_jumpt %3, %bb.1, implicit-def $pc
J2_jump %bb.2, implicit-def $pc
bb.1:
PS_jmpret $r31, implicit-def $pc
bb.2:
PS_jmpret $r31, implicit-def $pc
...