forked from OSchip/llvm-project
50 lines
1.7 KiB
LLVM
50 lines
1.7 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK-NOT: .sdata.4.g0,"aM"
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target triple = "hexagon-unknown--elf"
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%s.0 = type { i32 }
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@g0 = global %s.0 { i32 3 }, align 4 #0
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@g1 = global i32 0, align 4 #1
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@g2 = global %s.0* @g0, align 4 #2
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@g3 = global i32 0, align 4 #3
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@g4 = global i32 0, align 4 #4
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; Function Attrs: nounwind optsize
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define i32 @f0() #5 section ".text.main" {
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b0:
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%v0 = load i32, i32* @g3, align 4, !tbaa !4
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%v1 = add nsw i32 %v0, 1
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store i32 %v1, i32* @g3, align 4, !tbaa !4
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%v2 = load i8*, i8** bitcast (%s.0** @g2 to i8**), align 4, !tbaa !8
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%v3 = load i32, i32* @g1, align 4, !tbaa !10
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%v4 = getelementptr inbounds i8, i8* %v2, i32 %v3
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%v5 = bitcast i8* %v4 to i32*
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%v6 = load i32, i32* %v5, align 4, !tbaa !4
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store i32 %v6, i32* @g4, align 4, !tbaa !4
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store i32 1, i32* @g3, align 4, !tbaa !4
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ret i32 0
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}
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attributes #0 = { "linker_input_section"=".sdata.4.cccc" "linker_output_section"=".sdata.4" }
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attributes #1 = { "linker_input_section"=".sbss.4.np" "linker_output_section"=".sbss.4" }
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attributes #2 = { "linker_input_section"=".sdata.4.cp" "linker_output_section"=".sdata.4" }
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attributes #3 = { "linker_input_section"=".sbss.4.counter" "linker_output_section"=".sbss.4" }
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attributes #4 = { "linker_input_section"=".sbss.4.value" "linker_output_section"=".sbss.4" }
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attributes #5 = { nounwind optsize "target-cpu"="hexagonv55" }
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!llvm.module.flags = !{!0, !2}
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!0 = !{i32 6, !"Target CPU", !1}
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!1 = !{!"hexagonv55"}
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!2 = !{i32 6, !"Target Features", !3}
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!3 = !{!"-hvx"}
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!4 = !{!5, !5, i64 0}
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!5 = !{!"int", !6, i64 0}
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!6 = !{!"omnipotent char", !7, i64 0}
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!7 = !{!"Simple C/C++ TBAA"}
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!8 = !{!9, !9, i64 0}
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!9 = !{!"any pointer", !6, i64 0}
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!10 = !{!6, !6, i64 0}
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