forked from OSchip/llvm-project
343 lines
12 KiB
YAML
343 lines
12 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
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...
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# Generate the 3 operand vector bitfield extract instructions for 32-bit
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# operations only.
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---
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name: test_sbfx_s32_vvv
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legalized: true
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body: |
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bb.0.entry:
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liveins: $vgpr0, $vgpr1, $vgpr2
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; CHECK-LABEL: name: test_sbfx_s32_vvv
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
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; CHECK: [[SBFX:%[0-9]+]]:vgpr(s32) = G_SBFX [[COPY]], [[COPY1]](s32), [[COPY2]]
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; CHECK: $vgpr0 = COPY [[SBFX]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s32) = COPY $vgpr2
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%3:_(s32) = G_SBFX %0, %1(s32), %2
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$vgpr0 = COPY %3(s32)
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...
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---
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name: test_sbfx_s32_vii
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legalized: true
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body: |
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bb.0.entry:
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liveins: $vgpr0
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; CHECK-LABEL: name: test_sbfx_s32_vii
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 10
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; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
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; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
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; CHECK: [[SBFX:%[0-9]+]]:vgpr(s32) = G_SBFX [[COPY]], [[COPY1]](s32), [[COPY2]]
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; CHECK: $vgpr0 = COPY [[SBFX]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = G_CONSTANT i32 10
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%2:_(s32) = G_CONSTANT i32 4
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%3:_(s32) = G_SBFX %0, %1(s32), %2
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$vgpr0 = COPY %3(s32)
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...
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---
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name: test_sbfx_s32_vss
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legalized: true
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body: |
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bb.0.entry:
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liveins: $vgpr0, $sgpr0, $sgpr1
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; CHECK-LABEL: name: test_sbfx_s32_vss
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
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; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
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; CHECK: [[SBFX:%[0-9]+]]:vgpr(s32) = G_SBFX [[COPY]], [[COPY3]](s32), [[COPY4]]
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; CHECK: $vgpr0 = COPY [[SBFX]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $sgpr0
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%2:_(s32) = COPY $sgpr1
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%3:_(s32) = G_SBFX %0, %1(s32), %2
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$vgpr0 = COPY %3(s32)
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...
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# Expand to a sequence that implements the 64-bit bitfield extract using
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# shifts and masks.
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---
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name: test_sbfx_s64_vvv
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legalized: true
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body: |
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bb.0.entry:
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liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
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; CHECK-LABEL: name: test_sbfx_s64_vvv
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
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; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
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; CHECK: [[ASHR:%[0-9]+]]:vgpr(s64) = G_ASHR [[COPY]], [[COPY1]](s32)
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; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[ASHR]](s64)
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; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 64
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; CHECK: [[SUB:%[0-9]+]]:vgpr(s32) = G_SUB [[C]], [[COPY2]]
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; CHECK: [[SHL:%[0-9]+]]:vgpr(s64) = G_SHL [[ASHR]], [[SUB]](s32)
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; CHECK: [[ASHR1:%[0-9]+]]:vgpr(s64) = G_ASHR [[SHL]], [[SUB]](s32)
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; CHECK: $vgpr0_vgpr1 = COPY %3:vgpr(s64)
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%0:_(s64) = COPY $vgpr0_vgpr1
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%1:_(s32) = COPY $vgpr2
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%2:_(s32) = COPY $vgpr3
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%3:_(s64) = G_SBFX %0, %1(s32), %2
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$vgpr0_vgpr1 = COPY %3(s64)
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...
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---
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name: test_sbfx_s64_vss
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legalized: true
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body: |
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bb.0.entry:
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liveins: $vgpr0_vgpr1, $sgpr0, $sgpr1
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; CHECK-LABEL: name: test_sbfx_s64_vss
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; CHECK: [[ASHR:%[0-9]+]]:vgpr(s64) = G_ASHR [[COPY]], [[COPY1]](s32)
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; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[ASHR]](s64)
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; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 64
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; CHECK: [[SUB:%[0-9]+]]:vgpr(s32) = G_SUB [[C]], [[COPY2]]
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; CHECK: [[SHL:%[0-9]+]]:vgpr(s64) = G_SHL [[ASHR]], [[SUB]](s32)
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; CHECK: [[ASHR1:%[0-9]+]]:vgpr(s64) = G_ASHR [[SHL]], [[SUB]](s32)
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; CHECK: $vgpr0_vgpr1 = COPY %3:vgpr(s64)
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%0:_(s64) = COPY $vgpr0_vgpr1
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%1:_(s32) = COPY $vgpr0
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%2:_(s32) = COPY $vgpr1
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%3:_(s64) = G_SBFX %0, %1(s32), %2
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$vgpr0_vgpr1 = COPY %3(s64)
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...
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# If the offset and width are constants, use the 32-bit bitfield extract,
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# and merge to create a 64-bit result.
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---
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name: test_sbfx_s64_vii_small
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legalized: true
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body: |
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bb.0.entry:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: test_sbfx_s64_vii_small
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
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; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 31
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; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
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; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
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; CHECK: [[ASHR:%[0-9]+]]:vgpr(s64) = G_ASHR [[COPY]], [[COPY1]](s32)
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; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[ASHR]](s64)
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; CHECK: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
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; CHECK: [[SBFX:%[0-9]+]]:vgpr(s32) = G_SBFX [[UV]], [[C2]](s32), [[COPY2]]
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; CHECK: [[C3:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 31
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; CHECK: [[ASHR1:%[0-9]+]]:vgpr(s32) = G_ASHR [[SBFX]], [[C3]](s32)
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; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[SBFX]](s32), [[ASHR1]](s32)
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; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64)
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%0:_(s64) = COPY $vgpr0_vgpr1
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%1:_(s32) = G_CONSTANT i32 31
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%2:_(s32) = G_CONSTANT i32 4
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%3:_(s64) = G_SBFX %0, %1(s32), %2
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$vgpr0_vgpr1 = COPY %3(s64)
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...
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---
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name: test_sbfx_s64_vii_big
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legalized: true
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body: |
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bb.0.entry:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: test_sbfx_s64_vii_big
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
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; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 8
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; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 40
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
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; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
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; CHECK: [[ASHR:%[0-9]+]]:vgpr(s64) = G_ASHR [[COPY]], [[COPY1]](s32)
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; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[ASHR]](s64)
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; CHECK: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
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; CHECK: [[C3:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 8
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; CHECK: [[SBFX:%[0-9]+]]:vgpr(s32) = G_SBFX [[UV1]], [[C2]](s32), [[C3]]
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; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[UV]](s32), [[SBFX]](s32)
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; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64)
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%0:_(s64) = COPY $vgpr0_vgpr1
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%1:_(s32) = G_CONSTANT i32 8
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%2:_(s32) = G_CONSTANT i32 40
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%3:_(s64) = G_SBFX %0, %1(s32), %2
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$vgpr0_vgpr1 = COPY %3(s64)
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...
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---
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name: test_sbfx_s64_svv
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legalized: true
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body: |
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bb.0.entry:
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liveins: $sgpr0_sgpr1, $vgpr0, $vgpr1
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; CHECK-LABEL: name: test_sbfx_s64_svv
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; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; CHECK: [[COPY3:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
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; CHECK: [[ASHR:%[0-9]+]]:vgpr(s64) = G_ASHR [[COPY3]], [[COPY1]](s32)
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; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[ASHR]](s64)
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; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 64
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; CHECK: [[SUB:%[0-9]+]]:vgpr(s32) = G_SUB [[C]], [[COPY2]]
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; CHECK: [[SHL:%[0-9]+]]:vgpr(s64) = G_SHL [[ASHR]], [[SUB]](s32)
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; CHECK: [[ASHR1:%[0-9]+]]:vgpr(s64) = G_ASHR [[SHL]], [[SUB]](s32)
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; CHECK: $vgpr0_vgpr1 = COPY %3:vgpr(s64)
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%0:_(s64) = COPY $sgpr0_sgpr1
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%1:_(s32) = COPY $vgpr0
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%2:_(s32) = COPY $vgpr1
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%3:_(s64) = G_SBFX %0, %1(s32), %2
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$vgpr0_vgpr1 = COPY %3(s64)
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...
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# Expand to a sequence that combines the offset and width for the two operand
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# version of the 32-bit instruction.
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---
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name: test_sbfx_s32_svv
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legalized: true
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body: |
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bb.0.entry:
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liveins: $sgpr0, $vgpr0, $vgpr1
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; CHECK-LABEL: name: test_sbfx_s32_svv
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; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
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; CHECK: [[SBFX:%[0-9]+]]:vgpr(s32) = G_SBFX [[COPY3]], [[COPY1]](s32), [[COPY2]]
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; CHECK: $vgpr0 = COPY [[SBFX]](s32)
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $vgpr0
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%2:_(s32) = COPY $vgpr1
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%3:_(s32) = G_SBFX %0, %1(s32), %2
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$vgpr0 = COPY %3(s32)
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...
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---
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name: test_sbfx_s32_sss
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legalized: true
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body: |
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bb.0.entry:
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liveins: $sgpr0, $sgpr1, $sgpr3
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; CHECK-LABEL: name: test_sbfx_s32_sss
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; CHECK: [[COPY:%[0-9]+]]:sreg_32(s32) = COPY $sgpr0
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; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
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; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 63
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; CHECK: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[COPY1]], [[C]]
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; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16
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; CHECK: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY2]], [[C1]](s32)
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; CHECK: [[OR:%[0-9]+]]:sreg_32(s32) = G_OR [[AND]], [[SHL]]
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; CHECK: [[S_BFE_I32_:%[0-9]+]]:sreg_32(s32) = S_BFE_I32 [[COPY]](s32), [[OR]](s32), implicit-def $scc
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; CHECK: $sgpr0 = COPY [[S_BFE_I32_]](s32)
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $sgpr1
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%2:_(s32) = COPY $sgpr2
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%3:_(s32) = G_SBFX %0, %1(s32), %2
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$sgpr0 = COPY %3(s32)
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...
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---
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name: test_sbfx_s32_sii
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legalized: true
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body: |
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bb.0.entry:
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liveins: $sgpr0
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; CHECK-LABEL: name: test_sbfx_s32_sii
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; CHECK: [[COPY:%[0-9]+]]:sreg_32(s32) = COPY $sgpr0
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; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1
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; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 10
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; CHECK: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 63
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; CHECK: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[C]], [[C2]]
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; CHECK: [[C3:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16
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; CHECK: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C1]], [[C3]](s32)
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; CHECK: [[OR:%[0-9]+]]:sreg_32(s32) = G_OR [[AND]], [[SHL]]
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; CHECK: [[S_BFE_I32_:%[0-9]+]]:sreg_32(s32) = S_BFE_I32 [[COPY]](s32), [[OR]](s32), implicit-def $scc
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; CHECK: $sgpr0 = COPY [[S_BFE_I32_]](s32)
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = G_CONSTANT i32 1
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%2:_(s32) = G_CONSTANT i32 10
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%3:_(s32) = G_SBFX %0, %1(s32), %2
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$sgpr0 = COPY %3(s32)
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...
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# Expand to a sequence that combines the offset and width for the two operand
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# version of the 64-bit scalar instruction.
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---
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name: test_sbfx_s64_sss
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legalized: true
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body: |
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bb.0.entry:
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liveins: $sgpr0_sgpr1, $sgpr0, $sgpr1
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; CHECK-LABEL: name: test_sbfx_s64_sss
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; CHECK: [[COPY:%[0-9]+]]:sreg_64(s64) = COPY $sgpr0_sgpr1
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; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 63
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; CHECK: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[COPY1]], [[C]]
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; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16
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; CHECK: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY2]], [[C1]](s32)
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; CHECK: [[OR:%[0-9]+]]:sreg_32(s32) = G_OR [[AND]], [[SHL]]
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; CHECK: [[S_BFE_I64_:%[0-9]+]]:sreg_64(s64) = S_BFE_I64 [[COPY]](s64), [[OR]](s32), implicit-def $scc
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; CHECK: $sgpr0_sgpr1 = COPY [[S_BFE_I64_]](s64)
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%0:_(s64) = COPY $sgpr0_sgpr1
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%1:_(s32) = COPY $sgpr0
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%2:_(s32) = COPY $sgpr1
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%3:_(s64) = G_SBFX %0, %1(s32), %2
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$sgpr0_sgpr1 = COPY %3(s64)
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...
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---
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name: test_sbfx_s64_sii
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legalized: true
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body: |
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bb.0.entry:
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liveins: $sgpr0_sgpr1
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; CHECK-LABEL: name: test_sbfx_s64_sii
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; CHECK: [[COPY:%[0-9]+]]:sreg_64(s64) = COPY $sgpr0_sgpr1
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; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1
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; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 10
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; CHECK: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 63
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; CHECK: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[C]], [[C2]]
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; CHECK: [[C3:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16
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; CHECK: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C1]], [[C3]](s32)
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; CHECK: [[OR:%[0-9]+]]:sreg_32(s32) = G_OR [[AND]], [[SHL]]
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; CHECK: [[S_BFE_I64_:%[0-9]+]]:sreg_64(s64) = S_BFE_I64 [[COPY]](s64), [[OR]](s32), implicit-def $scc
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%0:_(s64) = COPY $sgpr0_sgpr1
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%1:_(s32) = G_CONSTANT i32 1
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%2:_(s32) = G_CONSTANT i32 10
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%3:_(s64) = G_SBFX %0, %1(s32), %2
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...
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